coreboot-gerrit January 2025

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[M] Change in coreboot[main]: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85822?usp=email ) Change subject: util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments ...................................................................... util/autoport/{bd82x6x,sandybridge}: Don't generate redundant comments Since the aliases are used and already contain the device name, there's reason to generate these in the first place. TEST=Ran autoport with logs from ASRock Z77 Extreme4. Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M util/autoport/bd82x6x.go M util/autoport/sandybridge.go 2 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85822/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 71b97d4..bd80901 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -124,29 +124,29 @@ "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), }, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal"}, }, } diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 29b57b4..552bd66 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -51,15 +51,15 @@ PCIController: true, ChildPCIBus: 0, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd"}, }, }, }, } - PutPCIDev(addr, "Host bridge") + PutPCIDev(addr, "") /* FIXME:XX some configs are unsupported. */ KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true -- To view, visit https://review.coreboot.org/c/coreboot/+/85822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019 Gerrit-Change-Number: 85822 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down
by Yidi Lin (Code Review) 01 Jan '25

01 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85751?usp=email ) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down ...................................................................... soc/mediatek/mt8196: Set SPMI-P SCL/SDA pins to pull-down The current Pull-Down capabilities of the SPMI are insufficient and require optimization. Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC side. It is done only once during the SPMI read check to fix SPMI clock calibration failure. TEST=Build pass BUG=b:361174333 Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85751 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index 91f9038..d00afe1 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -167,6 +167,9 @@ /* SPMI_P 14mA */ gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA); gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA); + /* SPMI-P set Pull-Down mode */ + gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); printk(BIOS_INFO, "%s done\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Angel Pons, Keith Hui. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: > Do you have to do anything special to make a PS/2 mouse work? Nope, it just works automatically in Devuan Daedalus (Linux 6.1 and Xfce 4.18). Kinda makes sense, since in vendor firmware there's also no setting to choose between a mouse and a keyboard. But on the other hand I recall seeing some other board in coreboot that had some issues with PS/2 mice connected like this. File src/mainboard/asrock/z77_extreme4/early_init.c: https://review.coreboot.org/c/coreboot/+/85772/comment/44bcd991_f8be791c?us… : PS12, Line 10: if (CONFIG(CONSOLE_SERIAL)) > The function will no-op itself if this config is not selected, so it's not necessary. Ack. Having the "if" here makes more sense imo. But yeah it's a bit redundant at the moment. Many other boards do this too, perhaps we should consistently have one style or the other. -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 12 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 12:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Enable x86_64
by Angel Pons (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email ) Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/85805/comment/26d14202_879bc3c6?us… : PS3, Line 514: 48 24 + 4 + 20 = 48 -- To view, visit https://review.coreboot.org/c/coreboot/+/85805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Gerrit-Change-Number: 85805 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 11:42:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer
by Angel Pons (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Nicholas Chin. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85790?usp=email ) Change subject: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff Gerrit-Change-Number: 85790 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 11:31:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/meteorlake: Add doc reference for thunderbolt port number
by Subrata Banik (Code Review) 01 Jan '25

01 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85820?usp=email ) Change subject: soc/intel/meteorlake: Add doc reference for thunderbolt port number ...................................................................... soc/intel/meteorlake: Add doc reference for thunderbolt port number Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other Device ID" IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 16. Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85820 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/pcie_rp.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 7cfe3ed..914520e 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -6,13 +6,15 @@ #include <soc/soc_info.h> /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) + * Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other + * Device ID" specifies that the first Thunderbolt PCIe root port number is 16. TBT's LCAP + * registers return port index which starts from 16 (usually for other PCIe root ports index + * starts from 1). Thus, keeping lcap_port_base 16 for TBT, so that coreboot's PCIe remapping + * logic can return a correct index (0-based). */ static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 16 }, { 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a Gerrit-Change-Number: 85820 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
by Subrata Banik (Code Review) 01 Jan '25

01 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 ...................................................................... soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 21. The previous offset of 0x10, inherited from Meteor Lake code, caused an issue that resulted in: - Temporary deactivation of Thunderbolt PCI devices during ramstage - Failure to generate critical ACPI SSDT power management data for the port This error led to instability in PCIe tunneling during power state transitions. Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 7 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 1b302fd..604e7af 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -5,13 +5,15 @@ #include <soc/pcie.h> /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) - */ + * Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" + * specifies that the first Thunderbolt PCIe root port number is 21. TBT's LCAP registers return + * port index which starts from 21 (usually for other PCIe root ports index starts from + * 1). Thus, keeping lcap_port_base 21 for TBT, so that coreboot's PCIe remapping logic can + * return a correct index (0-based). +*/ static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 21 }, { 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: cpu/x86/topology: Add module_id to CPU topology
by Subrata Banik (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Jérémy Compostella. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85577?usp=email ) Change subject: cpu/x86/topology: Add module_id to CPU topology ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27 Gerrit-Change-Number: 85577 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 07:08:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Drop unused MRC devicetree setting
by Keith Hui (Code Review) 01 Jan '25

01 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85821?usp=email to look at the new patch set (#2). Change subject: mb/asus/p8x7x-series: Drop unused MRC devicetree setting ...................................................................... mb/asus/p8x7x-series: Drop unused MRC devicetree setting Drop MRC setting usb3.hs_port_switch_mask that since commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree") mirrors xhci_switchable_ports and is no longer used separately. Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/85821/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Gerrit-Change-Number: 85821 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Keith Hui (Code Review) 01 Jan '25

01 Jan '25

Attention is currently required from: Angel Pons, Riku Viitanen. Keith Hui has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: Do you have to do anything special to make a PS/2 mouse work? File src/mainboard/asrock/z77_extreme4/early_init.c: https://review.coreboot.org/c/coreboot/+/85772/comment/24c44145_ad2c92d2?us… : PS12, Line 10: if (CONFIG(CONSOLE_SERIAL)) The function will no-op itself if this config is not selected, so it's not necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 12 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jan 2025 06:39:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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