coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Bill XIE. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/1bc26932_2bee7fae?us… : PS2, Line 77: {7, 34, 20, -1} > > Do you want manual control? […] Odd. As far as I understand these stuff I should have done everything right. I gotta ask for a hail-mary here. Can you temporarily go back to vendor BIOS, put it in a state where PCIEX1_2 works for you, and do an autoport-grade dump? I need to see what I missed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Wed, 22 Jan 2025 14:49:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Maximilian Brune (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Ana Carolina Cabral, Maximilian Brune. Hello Ana Carolina Cabral, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84500?usp=email to look at the new patch set (#3). Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... mb/amd/birman_plus: Update devicetree Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/devicetree_glinda.cb 2 files changed, 40 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84500/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86108?usp=email ) Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Gerrit-Change-Number: 86108 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 13:36:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rauru: Configure firmware display for eDP panel
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85952?usp=email ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Configure firmware display for eDP panel ...................................................................... mb/google/rauru: Configure firmware display for eDP panel Add eDP panel power-on sequences and initialize the display in the ramstage. The mt6373_set_vcn33_3_voltage function sets the voltage required to power on the eDP panel. TEST=Build pass, the firmware screen displays correctly. BUG=b:343351631, b:353464237 Signed-off-by: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85952 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/mainboard.c 2 files changed, 20 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index a686838..ae3ffb3 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -23,6 +23,8 @@ select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select MAINBOARD_HAS_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 817bcf2..f55da81 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -1,15 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <fw_config.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/bl31.h> +#include <soc/display.h> #include <soc/dpm_v2.h> #include <soc/gpio_common.h> #include <soc/i2c.h> #include <soc/msdc.h> +#include <soc/mt6373.h> #include <soc/pcie.h> #include <soc/spm_common.h> #include <soc/storage.h> @@ -70,6 +73,13 @@ gpio_output(GPIO_FP_RST_1V8_S3_L, 1); } +static void enable_display_power_rail(void) +{ + mt6373_init_pmif_arb(); + mt6373_enable_vcn33_3(true); + mt6373_set_vcn33_3_voltage(3300000); +} + enum mtk_storage_type mainboard_get_storage_type(void) { uint32_t index = storage_id(); @@ -96,6 +106,14 @@ static void mainboard_init(struct device *dev) { + if (display_init_required()) { + enable_display_power_rail(); + if (mtk_display_init() < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); + } + setup_usb_host(); power_on_fpmcu(); configure_audio(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036 Gerrit-Change-Number: 85952 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/rauru: Add panel driver in mainboard
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85951?usp=email ) Change subject: mb/google/rauru: Add panel driver in mainboard ...................................................................... mb/google/rauru: Add panel driver in mainboard Add panel driver in mainboard for rauru project and support OLED eDP panel. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/85951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/Makefile.mk M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h A src/mainboard/google/rauru/panel.c A src/mainboard/google/rauru/panel.h 7 files changed, 78 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 57e8c1b..a686838 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -33,6 +33,8 @@ select TPM_GOOGLE_TI50 if VBOOT select COMMONLIB_STORAGE select COMMONLIB_STORAGE_MMC + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI config MAINBOARD_DIR string diff --git a/src/mainboard/google/rauru/Makefile.mk b/src/mainboard/google/rauru/Makefile.mk index 98f5bbd..6ea1ffb8 100644 --- a/src/mainboard/google/rauru/Makefile.mk +++ b/src/mainboard/google/rauru/Makefile.mk @@ -10,4 +10,5 @@ ramstage-y += boardid.c ramstage-y += mainboard.c +ramstage-y += panel.c ramstage-y += regulator.c diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 6a34cb9..6a8431f 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -56,6 +56,12 @@ lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios)); else lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios)); + + struct lb_gpio edp_pwm_backlight_gpios[] = { + {GPIO_BL_PWM_1V8.id, ACTIVE_HIGH, -1, "PWM control"}, + {GPIO_AP_EDP_BKLTEN.id, ACTIVE_HIGH, -1, "backlight enable"}, + }; + lb_add_gpios(gpios, edp_pwm_backlight_gpios, ARRAY_SIZE(edp_pwm_backlight_gpios)); } int cr50_plat_irq_status(void) diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb index 1705dbe..55cc91c 100644 --- a/src/mainboard/google/rauru/devicetree.cb +++ b/src/mainboard/google/rauru/devicetree.cb @@ -8,6 +8,13 @@ end end +fw_config + field PANEL 18 21 + option DEFAULT 0 + option OLED 1 + end +end + chip soc/mediatek/mt8196 device cpu_cluster 0 on end diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index c1c5b4b..f35135c 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -15,6 +15,11 @@ #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) +#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) + +#define GPIO_AP_EDP_BKLTEN GPIO(PERIPHERAL_EN4) +#define GPIO_EN_PP3300_EDP_X GPIO(PERIPHERAL_EN2) +#define GPIO_EDP_HPD_1V8 GPIO(EINT13) #define GPIO_I2SI4_BCK GPIO(I2SIN1_BCK) #define GPIO_I2SI4_LRCK GPIO(I2SIN1_LRCK) diff --git a/src/mainboard/google/rauru/panel.c b/src/mainboard/google/rauru/panel.c new file mode 100644 index 0000000..8564f4c --- /dev/null +++ b/src/mainboard/google/rauru/panel.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <fw_config.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> + +#include "gpio.h" +#include "panel.h" + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_backlight(void) +{ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); +} + +static void power_on_panel(void) +{ + gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EINT13, EDP_TX_HPD)); +} + +static struct panel_description panel = { + .configure_backlight = configure_backlight, + .power_on = power_on_panel, + .disp_path = DISP_PATH_EDP, + .orientation = LB_FB_ORIENTATION_NORMAL, +}; + +static void power_on_oled_panel(void) +{ + gpio_output(GPIO_EN_PP3300_EDP_X, 1); + gpio_set_mode(GPIO_EDP_HPD_1V8, GPIO_FUNC(EINT13, EDP_TX_HPD)); +} + +static struct panel_description oled_panel = { + .configure_backlight = configure_backlight, + .power_on = power_on_oled_panel, + .disp_path = DISP_PATH_EDP, + .orientation = LB_FB_ORIENTATION_NORMAL, +}; + +struct panel_description *get_active_panel(void) +{ + if (fw_config_probe(FW_CONFIG(PANEL, OLED))) { + return &oled_panel; + } + return &panel; +} diff --git a/src/mainboard/google/rauru/panel.h b/src/mainboard/google/rauru/panel.h new file mode 100644 index 0000000..9b18f1d --- /dev/null +++ b/src/mainboard/google/rauru/panel.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_RAURU_PANEL_H__ +#define __MAINBOARD_GOOGLE_RAURU_PANEL_H__ + +struct panel_description *get_oled_description(void); + +#endif /* __MAINBOARD_GOOGLE_RAURU_PANEL_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86108?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved ...................................................................... soc/mediatek/mt8196: Correct the region size for mcufw_reserved Adjust the allocated region size for mcufw_reserved from 52K to 68K. TEST=Build pass. BUG=b:390334489 Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86108/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Gerrit-Change-Number: 86108 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: payloads/LinuxBoot: Build x86_64 with host toolchain
by Maximilian Brune (Code Review) 22 Jan '25

22 Jan '25

Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83990?usp=email ) Change subject: payloads/LinuxBoot: Build x86_64 with host toolchain ...................................................................... Patch Set 4: (1 comment) File payloads/external/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83990/comment/7afd6763_15ac066d?us… : PS4, Line 393: ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),y) : ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"") : # use coreboots cross toolchain : CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y)) : endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH : else # CONFIG_LINUXBOOT_CROSS_COMPILE : $(warning "Using host toolchain to build Linuxboot") : endif # CONFIG_LINUXBOOT_CROSS_COMPIL > shouldn't be :? […] If CROSS_COMPILE is "no" we use the host toolchain. If CROSS_COMPILE is "yes" but we didn't specify a custom cross compile toolchain we want to use the coreboot cross toolchain. If CROSS_COMPILE is "yes" but we specified a custom cross compile toolchain we chose that one. So the only case in which host toolchain is used is the one in which CROSS_COMPILE is not set. Maybe I mixed something up, but if I did, I don't see it right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/83990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf56d6991d79f629e9ba8c901b441d81921d594 Gerrit-Change-Number: 83990 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 22 Jan 2025 13:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: ec/dasharo: Add dependancy to EC_DASHARO_EC_FLASH_SIZE
by Sean Rhodes (Code Review) 22 Jan '25

22 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86109?usp=email ) Change subject: ec/dasharo: Add dependancy to EC_DASHARO_EC_FLASH_SIZE ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icce0c7a31c89cea5e7bf89770dedbf82ff56170b Gerrit-Change-Number: 86109 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 22 Jan 2025 13:10:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86108?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved ...................................................................... soc/mediatek/mt8196: Correct the region size for mcufw_reserved Adjust the allocated region size for mcufw_reserved from 52K to 68K. TEST=Build pass. BUG=b:390334489 Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 --- M src/soc/mediatek/mt8196/include/soc/memlayout.ld 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86108/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1 Gerrit-Change-Number: 86108 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: superio/nuvoton: Add NCT5535D
by Keith Hui (Code Review) 22 Jan '25

22 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85834?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: superio/nuvoton: Add NCT5535D ...................................................................... superio/nuvoton: Add NCT5535D NCT5535D is a 64-pin LPC super I/O chip found on many Asus P8x7x series mainboards with no publicly available datasheet. However, based on mb/asus/p8z77-v_lx2, this chip can probably be driven like a NCT6779D, on which this is based. Devices not present on this chip compared to NCT6779D are parallel port, serial port B, GPIOs 0,1,3,6. p8z77-v_lx2 still builds once modified for this chip, but is not tested further. Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/superio/nuvoton/nct5535d/Kconfig A src/superio/nuvoton/nct5535d/Makefile.mk A src/superio/nuvoton/nct5535d/acpi/superio.asl A src/superio/nuvoton/nct5535d/nct5535d.h A src/superio/nuvoton/nct5535d/superio.c 5 files changed, 301 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85834/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Gerrit-Change-Number: 85834 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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