coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86104?usp=email to look at the new patch set (#2). Change subject: soc/intel/pantherlake: Add platform debug option for FSP ...................................................................... soc/intel/pantherlake: Add platform debug option for FSP Previously, DCI was enabled unconditionally, which could interfere with the USB data path when connected behind a powered hub and/or servo v4.1 debug connector. This patch sets DciEn parameter based on the selected platform debug option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is set to 0. BUG=b:384453901 TEST=Able to boot google/fatcat. Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86104/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Gerrit-Change-Number: 86104 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption t...
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86105?usp=email ) Change subject: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready" ...................................................................... Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready" This default configuration caused a problem where USB devices connected behind a powered hub and/or Servo v4.1 were not detected. Reverting this change restores the previous behavior where Trace Hub and DCI are disabled by default, resolving the USB detection issue. BUG=b:384453901 TEST=Able to boot google/fatcat using USB storage behind servo v4.1 This reverts commit 1ed186fbff84386e0196dd30dd7bc89b8fec2cec. Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/86105/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 4f6f658..dde401b 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -95,7 +95,6 @@ select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP - select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION -- To view, visit https://review.coreboot.org/c/coreboot/+/86105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d Gerrit-Change-Number: 86105 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add platform debug option for FSP
by Subrata Banik (Code Review) 22 Jan '25

22 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86104?usp=email ) Change subject: soc/intel/pantherlake: Add platform debug option for FSP ...................................................................... soc/intel/pantherlake: Add platform debug option for FSP Previously, DCI was enabled unconditionally, which could interfere with the USB data path when connected behind a powered hub and/or servo v4.1 debug connector. This patch sets DciEn parameter based on the selected platform debug option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is set to 0. BUG=b:384453901 TEST=Able to boot google/fatcat. Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86104/1 diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 5846037..aed07bf 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -121,6 +121,24 @@ | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; + +/* Platform Debug Option using HW interface + * + * 0: Disabled, + * 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix, + * 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix, + * 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional + * low power state, + * 7: User needs to configure Advanced Debug Settings manually. (only applicable for devices + * with BIOS Setup Menu option present. + */ +enum platform_hw_debug_option { + HW_DEBUG_DISABLE = 0, + HW_DEBUG_TRACEHUB_ACTIVE = BIT(1), + HW_DEBUG_TRACEHUB_READY = BIT(2), + HW_DEBUG_TRACEHUB_POWEROFF = BIT(2) | BIT(1), +}; + /* * As per definition from FSP header: * - [0] for IA diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 033c4ea..2bb4d21 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -253,7 +253,17 @@ m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT; m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); - m_cfg->DciEn = 1; + + switch (CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT) { + case HW_DEBUG_TRACEHUB_ACTIVE: + case HW_DEBUG_TRACEHUB_READY: + case HW_DEBUG_TRACEHUB_POWEROFF: + m_cfg->DciEn = 1; + break; + case HW_DEBUG_DISABLE: + m_cfg->DciEn = 0; + break; + } } static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/86104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Gerrit-Change-Number: 86104 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 11:09:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/telith: Configure Acoustic noise mitigation
by Eric Lai (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Jian Tong, Kapil Porwal, Kun Liu, Nick Vaccaro. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/86103?usp=email ) Change subject: mb/google/nissa/var/telith: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57055cdfc9377ba141c620dd4e9301f6e7601629 Gerrit-Change-Number: 86103 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 11:02:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/LinuxBoot: Build x86_64 with host toolchain
by Elyes Haouas (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Maximilian Brune. Elyes Haouas has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83990?usp=email ) Change subject: payloads/LinuxBoot: Build x86_64 with host toolchain ...................................................................... Patch Set 4: (1 comment) File payloads/external/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83990/comment/bc200a3a_43983acc?us… : PS4, Line 393: ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),y) : ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"") : # use coreboots cross toolchain : CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y)) : endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH : else # CONFIG_LINUXBOOT_CROSS_COMPILE : $(warning "Using host toolchain to build Linuxboot") : endif # CONFIG_LINUXBOOT_CROSS_COMPIL shouldn't be :? ```suggestion ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),y) ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"") # use coreboots cross toolchain CONFIG_LINUXBOOT_CROSS_COMPILE_PATH=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y)) else # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH $(warning "Using host toolchain to build Linuxboot") endif # CONFIG_LINUXBOOT_CROSS_COMPILE_PATH endif # CONFIG_LINUXBOOT_CROSS_COMPILE ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf56d6991d79f629e9ba8c901b441d81921d594 Gerrit-Change-Number: 83990 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 10:55:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Shunxi Zhang (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Shunxi Zhang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 11: Code-Review+1 (3 comments) File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/53870936_7f2eb967?us… : PS10, Line 13: #include <soc/mt6685.h> > remove will update https://review.coreboot.org/c/coreboot/+/85978/comment/3818a9bf_8ca49673?us… : PS10, Line 14: #include <soc/pmif.h> : #include <soc/spmi.h> > Do we still need these two headers after using mt6685 API ? will update https://review.coreboot.org/c/coreboot/+/85978/comment/3bbffc1a_160b6ba7?us… : PS10, Line 90: config_interface(RG_FQMTR_TCKSEL, FQMTR_DCXO26M_EN | measure_src, : RG_FQMTR_TCKSEL_MASK, RG_FQMTR_TCKSEL_SHIFT); > `config_interface(0x546, (1ul << (4)) | measure_src, 0x7, 0);` […] will update -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 10:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/corsola: Increase ANX7625 data trail time
by Xin Ji (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86101?usp=email to look at the new patch set (#3). Change subject: mb/google/corsola: Increase ANX7625 data trail time ...................................................................... mb/google/corsola: Increase ANX7625 data trail time Currently, the eDP panel has display shift issue. This issue caused by shorter HS-trail time. Based on hardware design ANX7625 requires more HS-trail time to finish mipi data packet decoding before enter LP mode. So increase HS-trail time to avoid effect of entering LP mode. BUG=id:391304679 BRANCH=corsola TEST=Display is normal on corsola Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Signed-off-by: Xin Ji <xji(a)analogix.corp-partner.google.com> --- M src/mainboard/google/corsola/panel_anx7625.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86101/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 3 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Jarried Lin (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Shunxi Zhang, Yu-Ping Wu. Hello Hung-Te Lin, Shunxi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85978?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Shunxi Zhang, Code-Review+1 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... soc/mediatek/mt8196: Add RTC driver Add RTC drivers for MT6685. TEST=build pass. BUG=b:317009620 Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Signed-off-by: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc_osc_init.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/mt6685_hw.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h A src/soc/mediatek/mt8196/include/soc/rtc.h A src/soc/mediatek/mt8196/mt6685_rtc.c 8 files changed, 2,119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85978/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/corsola: Increase ANX7625 data trail time
by Xin Ji (Code Review) 22 Jan '25

22 Jan '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Xin Ji has posted comments on this change by Xin Ji. ( https://review.coreboot.org/c/coreboot/+/86101?usp=email ) Change subject: mb/google/corsola: Increase ANX7625 data trail time ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86101/comment/73d61087_bc6a2090?us… : PS1, Line 7: fine tune the data lane trail > More specific: […] OK https://review.coreboot.org/c/coreboot/+/86101/comment/21d69099_6b7f9521?us… : PS1, Line 8: > Please start by describing the problem, like: Currently, the display flickers. OK https://review.coreboot.org/c/coreboot/+/86101/comment/31622428_9f3fee29?us… : PS1, Line 9: ANX7625 requires customized hs_da_trail time > Why? According to the schematics? I'll add more description. https://review.coreboot.org/c/coreboot/+/86101/comment/70376854_5f9c0a86?us… : PS1, Line 9: override the : data trail for ANX7625 > What is the current value, and what is the new value? Why is the new value correct? I'm not sure current value, need ask MTK. File src/mainboard/google/corsola/panel_anx7625.c: https://review.coreboot.org/c/coreboot/+/86101/comment/27a4cc49_a1c289a1?us… : PS1, Line 69: timing->da_hs_trail += 9; > Maybe better use the absolute value, or does it always need to be increased by nine? I cannot use the absolute value, I'm not sure the original value. -- To view, visit https://review.coreboot.org/c/coreboot/+/86101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57 Gerrit-Change-Number: 86101 Gerrit-PatchSet: 1 Gerrit-Owner: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 22 Jan 2025 10:36:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit January 2025