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Change subject: soc/mediatek/mt8196: Fix MT6363 buck5 enablement
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................
Patch Set 3:
(3 comments)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/85865/comment/5449ecee_f76b8664?us… :
PS2, Line 112:
> Remove extra spaces here
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/85865/comment/564fc216_666d8ac9?us… :
PS2, Line 89: /*M
> Add space between comment symbols and text, and correct 'disabled'. […]
Done
https://review.coreboot.org/c/coreboot/+/85865/comment/edeaec2c_6701851b?us… :
PS2, Line 90: used
> using?
Done
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................
soc/amd/cezanne: Disable I2S internal clock based on mainboard config
Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
2 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/3
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
Patch Set 3: Code-Review+2
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
util/chromeos/crosfirmware: Add special handling for REEF board
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85873/3
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
Patch Set 2:
(1 comment)
File util/chromeos/crosfirmware.sh:
https://review.coreboot.org/c/coreboot/+/85873/comment/6f5602eb_dc239c1f?us… :
PS1, Line 110: \
> While on it, maybe put it in between single quotation marks?
Done
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85873?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
util/chromeos/crosfirmware: Add special handling for REEF board
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85873/2
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Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/common/dp/dptx_hal_common.c:
https://review.coreboot.org/c/coreboot/+/85861/comment/ece6cf49_15ee11fb?us… :
PS3, Line 115: DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7);
> I define `DP_CLRSETBITS` on mt8196 like this. […]
Okay, then that will also work. However, to determine whether to use your `DP_CLRSETBITS` solution or my suggestion about `mtk_dp_write_byte`, I think we need to understand why MT8196 doesn't need those `DP_TX_TOP_APB_WSTRB` writes (I see no references to `mtk_dp_write_byte` in MT8196's code).
- If the original `mtk_dp_write_byte` flow (containing `DP_TX_TOP_APB_WSTRB` writes) makes sense for MT8196 and MT8196 happens to not need that function, then I'm fine with using `DP_CLRSETBITS`.
- Otherwise, if `mtk_dp_write_byte` doesn't make sense for MT8196, then we should define a separate `mtk_dp_write_byte` (without `DP_TX_TOP_APB_WSTRB`), as I suggested above.
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Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/common/dp/dptx_common.c:
https://review.coreboot.org/c/coreboot/+/85860/comment/d70e8801_d91fe81b?us… :
PS4, Line 281: union misc_t dptx_misc;
> Do you suggest fixing it in a separate patch or in the same patch ?
Separate patch.
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