coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Work around DPR silicon bug
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85829?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Work around DPR silicon bug ...................................................................... soc/intel/xeon_sp: Work around DPR silicon bug On first batch of Intel Xeon-SP 10nm CPU the DPR register is affected by a silicon bug, where the TOP bits read as 0, which isn't possible according to the EDS. Currently the code also assumes that it's never zero and calculates the DPR size using the assigned address. By using 0 as TOP address it overflows and breaks boot due to an overly large MMIO window. Add a check for the silicon bug and use TSEG base like it's already done on Snow Ridge, which is also a 10nm Xeon CPU affected by the same bug. Fixes negative size being calculated for DPR. TEST: Xeon ICX-SP boots to Linux. Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/snowridge/systemagent.c M src/soc/intel/xeon_sp/uncore.c 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85829/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Xeon ICX-SP support
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85845?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ...................................................................... soc/intel/xeon_sp: Add Xeon ICX-SP support Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested are dual socket systems with a LBG PCH. The WhitleyFSP, that is being used here, never has been validated in API mode and has several flaws: - CPU PCIe ports MUST be disabled - QPI links MUST run at degraded speeds Currently uses the SPR ACPI code. TEST: Boots to Linux userspace. No errors in coreboot or dmesg visible. TODO: Merge with SPR code base. Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/xeon_sp/Makefile.mk A src/soc/intel/xeon_sp/icx/Kconfig A src/soc/intel/xeon_sp/icx/Makefile.mk A src/soc/intel/xeon_sp/icx/chip.c A src/soc/intel/xeon_sp/icx/chip.h A src/soc/intel/xeon_sp/icx/chipset.cb A src/soc/intel/xeon_sp/icx/cpu.c A src/soc/intel/xeon_sp/icx/hob_display.c A src/soc/intel/xeon_sp/icx/include/soc/pci_devs.h A src/soc/intel/xeon_sp/icx/include/soc/soc_msr.h A src/soc/intel/xeon_sp/icx/include/soc/soc_util.h A src/soc/intel/xeon_sp/icx/ramstage.c A src/soc/intel/xeon_sp/icx/reset.c A src/soc/intel/xeon_sp/icx/romstage.c A src/soc/intel/xeon_sp/icx/soc_acpi.c A src/soc/intel/xeon_sp/icx/soc_util.c A src/soc/intel/xeon_sp/icx/upd_display.c 18 files changed, 1,457 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85845/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Gerrit-Change-Number: 85845 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Work around FSP bug
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Maximilian Brune, Paul Menzel. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85789?usp=email ) Change subject: cpu/x86/64bit/mode_switch: Work around FSP bug ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85789/comment/e19f4a47_2c67a71e?us… : PS2, Line 7: Add workaround for FSP bug > Work around FSP bug Done https://review.coreboot.org/c/coreboot/+/85789/comment/f55d940a_d3a94caa?us… : PS2, Line 9: backup > back up Done https://review.coreboot.org/c/coreboot/+/85789/comment/84b52770_d8353021?us… : PS2, Line 9: FSP > Please add the version. Done https://review.coreboot.org/c/coreboot/+/85789/comment/ca200146_2dfe0ae6?us… : PS2, Line 10: it's > its Done https://review.coreboot.org/c/coreboot/+/85789/comment/c0e8e9f2_6ffae02f?us… : PS2, Line 14: workaround > Work around this issue by: Done https://review.coreboot.org/c/coreboot/+/85789/comment/e6bc9578_84ffd439?us… : PS2, Line 16: Backup > Back up Done File src/cpu/x86/64bit/mode_switch.S: https://review.coreboot.org/c/coreboot/+/85789/comment/314e0a34_6998eccf?us… : PS2, Line 30: push $0 : push $0 > nit: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 04 Jan 2025 09:26:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Work around FSP bug
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Paul Menzel. Hello Arthur Heymans, Jérémy Compostella, Maximilian Brune, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85789?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) Change subject: cpu/x86/64bit/mode_switch: Work around FSP bug ...................................................................... cpu/x86/64bit/mode_switch: Work around FSP bug FSP, that is build against EDK2 2018 or newer, is able to back up and restore the bootloader IDT on entry/exit. Even though it sets up its own IDT, FSP checks the bootloader IDT size and deadloops without warning if it's too big. On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus x86_32 FSP might die on entry. Work around this issue by: * Back up and restore the IDT in protected_mode_call_wrapper * Load zero IDT in protected mode before jumping to function TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with exceptions in romstage enabled. Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch.S 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/85789/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/f7a3d28b_22297bf6?us… : PS3, Line 7: Add fix for DPR silicon bug > Fix DPR silicon bug Will rephrase to workaround, the silicon cannot be fixed https://review.coreboot.org/c/coreboot/+/85829/comment/b7bbac37_1037f241?us… : PS3, Line 24: > Have you reported this bug to Intel, and are they going to release an errata? Unrelated. -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 08:09:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 04 Jan '25

04 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85850?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W pl1:15w(default) -> 22w 2.update the DPTF parameters were defined by the thermal team. BUG=b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/85850/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 3c04da5..9d91a45 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -152,7 +152,11 @@ .tdp_pl2_override = 25, .tdp_pl4 = 78, }" - + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -165,11 +169,11 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000), }" ## Critical Policy @@ -181,7 +185,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 6000, + .max_power = 13000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -197,8 +201,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 1500 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -222,11 +226,11 @@ .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(44, 61), + TEMP_PCT(42, 54), + TEMP_PCT(40, 45), + TEMP_PCT(38, 38), + TEMP_PCT(36, 25), } }, [1] = { @@ -277,7 +281,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -293,8 +297,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 2000 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -302,14 +306,14 @@ ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 100, 4000, 220, 1640, }, - [1] = { 90, 3700, 220, 1640, }, - [2] = { 80, 3500, 180, 1310, }, - [3] = { 70, 3300, 145, 1030, }, + [1] = { 90, 4100, 220, 1640, }, + [2] = { 80, 3800, 180, 1310, }, + [3] = { 70, 3500, 145, 1030, }, [4] = { 60, 3100, 115, 765, }, [5] = { 50, 2800, 90, 545, }, - [6] = { 40, 2500, 55, 365, }, - [7] = { 30, 2100, 30, 220, }, - [8] = { 20, 1500, 15, 120, }, + [6] = { 40, 2400, 55, 365, }, + [7] = { 30, 1900, 30, 220, }, + [8] = { 20, 1400, 15, 120, }, [9] = { 0, 0, 0, 50, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/85850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Gerrit-Change-Number: 85850 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85849?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 2.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85849/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Gerrit-Change-Number: 85849 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 04 Jan '25

04 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85849?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 2.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85849/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d2ad383..9ee5871 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -152,7 +152,11 @@ .tdp_pl2_override = 25, .tdp_pl4 = 78, }" - + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -165,11 +169,11 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000), }" ## Critical Policy @@ -181,7 +185,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 6000, + .max_power = 13000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -197,8 +201,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 1500 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -222,11 +226,11 @@ .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(44, 61), + TEMP_PCT(42, 54), + TEMP_PCT(40, 45), + TEMP_PCT(38, 38), + TEMP_PCT(36, 25), } }, [1] = { @@ -277,7 +281,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -293,8 +297,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 2000 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -302,14 +306,14 @@ ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 100, 4000, 220, 1640, }, - [1] = { 90, 3700, 220, 1640, }, - [2] = { 80, 3500, 180, 1310, }, - [3] = { 70, 3300, 145, 1030, }, + [1] = { 90, 4100, 220, 1640, }, + [2] = { 80, 3800, 180, 1310, }, + [3] = { 70, 3500, 145, 1030, }, [4] = { 60, 3100, 115, 765, }, [5] = { 50, 2800, 90, 545, }, - [6] = { 40, 2500, 55, 365, }, - [7] = { 30, 2100, 30, 220, }, - [8] = { 20, 1500, 15, 120, }, + [6] = { 40, 2400, 55, 365, }, + [7] = { 30, 1900, 30, 220, }, + [8] = { 20, 1400, 15, 120, }, [9] = { 0, 0, 0, 50, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/85849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Gerrit-Change-Number: 85849 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85848?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 1.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85848/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Gerrit-Change-Number: 85848 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85848?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(defualt) -> 22W 1.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85848/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Gerrit-Change-Number: 85848 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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