coreboot-gerrit January 2025

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Alicja Michalska (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Angel Pons, Felix Singer, Nicholas Chin. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email ) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Patch Set 8: (8 comments) File Documentation/mainboard/erying/tgl/tgl_matx.md: https://review.coreboot.org/c/coreboot/+/81611/comment/817aca04_2583b20a?us… : PS7, Line 37: By going to `Chipset -> Include CPU microcode in CBFS (Include external microcode binary)`. > Markdown ignores new lines without a blank line in between, so this […] ack :) https://review.coreboot.org/c/coreboot/+/81611/comment/36f8c647_5f32e552?us… : PS7, Line 66: If you're using [flashrom] or [flashprog] (fork of flashrom), you can skip extracting `SI_BIOS` and `SI_ME` regions from your ROM, and flash coreboot to `SI_BIOS` region by issuing the following command: > Please reflow to 72 characters Done https://review.coreboot.org/c/coreboot/+/81611/comment/f6ac8a98_a1c43ef0?us… : PS7, Line 112: `modprobe it87 force_id=0x8603 > Missing closing backtick? […] yup, thanks! https://review.coreboot.org/c/coreboot/+/81611/comment/a6be6789_5b76f940?us… : PS7, Line 117: - Intel Flash Descriptor (IFD) is required if you wish to flash the entire chip. : - Intel Management Engine blob is required if you wish to flash the entire chip. > These render a bit awkwardly (the bullets are at the same indent level […] Done https://review.coreboot.org/c/coreboot/+/81611/comment/99644cf4_4b8f904a?us… : PS7, Line 119: Both blobs included in `3rdparty/blobs` repository have been extracted from vendor's firmware. : IFD region has been modified using `ifdtool` to flip `MeAltDisable` flag. > As above; this renders as part of the bullet point about the Intel ME. […] I've re-phrased it a little bit and aligned to indentation (which makes sense IMO, as it's a part of point 1) https://review.coreboot.org/c/coreboot/+/81611/comment/13f2ca18_f59e2b06?us… : PS7, Line 123: It is possible to replace Winbond 16MB chip with 32MB equivalent, which would allow you to use LinuxBoot or implement RO + A/B VBOOT update scheme. > This renders on the same line as Modifications. […] Done https://review.coreboot.org/c/coreboot/+/81611/comment/3e46bf45_f69d7df7?us… : PS7, Line 126: If you are using an external graphics card (AMD Radeon, Nvidia GeForce, Intel Arc), you will see output in your OS as soon as kernel initializes the card (called "modprobing" in Linux) regardless of payload you chose. : This board have been tested with: : - EDK2 : - U-Boot : - LinuxBoot (U-Root + Linux kernel) > As above. I'd recommend indenting this to the same level as "Payload and ..." (i.e. […] Done https://review.coreboot.org/c/coreboot/+/81611/comment/0b4739ab_40ac145d?us… : PS7, Line 122: 2. Modifications : It is possible to replace Winbond 16MB chip with 32MB equivalent, which would allow you to use LinuxBoot or implement RO + A/B VBOOT update scheme. : : 3. Payload and pre-OS display output : If you are using an external graphics card (AMD Radeon, Nvidia GeForce, Intel Arc), you will see output in your OS as soon as kernel initializes the card (called "modprobing" in Linux) regardless of payload you chose. : This board have been tested with: : - EDK2 : - U-Boot : - LinuxBoot (U-Root + Linux kernel) : : If you would like to see output on your iGPU before that stage (for picking a different boot medium or toggling Secure Boot setting), you need to use [MrChromebox's EDK2] fork and include [GOP driver] for TigerLake iGPU in your build. : This will allow you to see output of EDK2 (payload, boot picker) on your monitor connected to iGPU. : : If you're planning to primarly use an external card, disable iGPU by toggling `Chipset -> Disable Integrated GFX Controller (0:2:0)` and use [elly's EDK2] tree. : In order to enable loading OpROMs from PCIe devices, go to `Payload -> edk2 additional custom build parameters` and add the string: `-D LOAD_OPTION_ROMS=TRUE`. : This functionality has been tested with following GPUs, with following results: : - Nvidia GeForce RTX3080;RTX3090: Works perfectly : - AMD Radeon RX6600XT;RX7800XT: Works with ReBAR disabled, no output in EDK2 with ReBAR enabled : - Intel Arc A580: Works with ReBAR disabled, glitched framebuffer before modprobing > Please reflow to 72 characters Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 8 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Jan 2025 21:27:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Alicja Michalska (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Alicja Michalska, Angel Pons, Felix Singer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81611?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Documentation: Add Erying Polestar G613 Pro Document the board and process of building/flashing coreboot on it. Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A Documentation/mainboard/erying/tgl/tgl_matx.md M Documentation/mainboard/index.md 2 files changed, 211 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81611/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 8 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/starlabs/lite: Put options in CFR cbtable
by Sean Rhodes (Code Review) 05 Jan '25

05 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/76583?usp=email ) Change subject: mb/starlabs/lite: Put options in CFR cbtable ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/76583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42ae5b35e6b53b5a13ec3f80180f4955db9b6ce2 Gerrit-Change-Number: 76583 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2025 20:17:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Only include battery ACPI for systems with a battery
by Sean Rhodes (Code Review) 05 Jan '25

05 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85716?usp=email ) Change subject: ec/starlabs/merlin: Only include battery ACPI for systems with a battery ...................................................................... Patch Set 5: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I381714887f4319d8e1a25c1e493ba03631cbf082 Gerrit-Change-Number: 85716 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2025 20:17:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Only include battery ACPI for systems with a battery
by Sean Rhodes (Code Review) 05 Jan '25

05 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85716?usp=email ) Change subject: ec/starlabs/merlin: Only include battery ACPI for systems with a battery ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I381714887f4319d8e1a25c1e493ba03631cbf082 Gerrit-Change-Number: 85716 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2025 20:17:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/erying/tgl: Remove unnecessary include in bootblock
by Nicholas Chin (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Alicja Michalska. Nicholas Chin has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85856?usp=email ) Change subject: mb/erying/tgl: Remove unnecessary include in bootblock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52de6b6ea6eb88ddb96e353161f365cc0fda807c Gerrit-Change-Number: 85856 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Jan 2025 19:15:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/erying/tgl: Remove unnecessary include in bootblock
by Alicja Michalska (Code Review) 05 Jan '25

05 Jan '25

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85856?usp=email ) Change subject: mb/erying/tgl: Remove unnecessary include in bootblock ...................................................................... mb/erying/tgl: Remove unnecessary include in bootblock Change-Id: I52de6b6ea6eb88ddb96e353161f365cc0fda807c Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/mainboard/erying/tgl/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/85856/1 diff --git a/src/mainboard/erying/tgl/bootblock.c b/src/mainboard/erying/tgl/bootblock.c index 15be8ce..3f51096 100644 --- a/src/mainboard/erying/tgl/bootblock.c +++ b/src/mainboard/erying/tgl/bootblock.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8613e/it8613e.h> -#include <gpio.h> #define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) -- To view, visit https://review.coreboot.org/c/coreboot/+/85856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52de6b6ea6eb88ddb96e353161f365cc0fda807c Gerrit-Change-Number: 85856 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[XS] Change in coreboot[main]: opensbi is a burden!
by Elyes Haouas (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85732?usp=email to look at the new patch set (#10). Change subject: opensbi is a burden! ...................................................................... opensbi is a burden! Updating from commit id 5019fd124b4c: 2022-09-01 16:53:28 +0530 - (include: sbi: Reduce includes in sbi_pmu.h) to commit id bd613dd92113: 2024-12-24 15:28:18 +0530 - (include: Bump-up version to 1.6) This brings in 713 new commits. Change-Id: Ic050c7b8dc2e202ee3b7fe07c749181c0845f0e7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/opensbi 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85732/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic050c7b8dc2e202ee3b7fe07c749181c0845f0e7 Gerrit-Change-Number: 85732 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: commonlib/include/commonlib: Add volatile qualifier
by Patrick Rudolph (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85855?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: commonlib/include/commonlib: Add volatile qualifier ...................................................................... commonlib/include/commonlib: Add volatile qualifier With the introduction of the stack canary breakpoint QEMU uncovered a different bug within coreboot. Currently the compiler optimizes over aggressively inline functions and memory stores. That also affects write_at_ble8(), which is supposed to store a single byte at time. The compiler however optimizes multiple byte stores into a single wider (and possibly unaligned) store operation. This can be seen in the emited assembly code of write_le16(), as used to install the EBDA: 401348a: 66 c7 04 25 13 04 00 movw $0x400,0x413 4013491: 00 00 04 Make sure that the compiler does not optimize multiple calls to write_at_ble8() by adding the volatile qualifier. The emitted assembly code of the same function changes to: 401394c: c6 04 25 13 04 00 00 movb $0x0,0x413 4013953: 00 4013954: c6 04 25 14 04 00 00 movb $0x4,0x414 401395b: 04 Fixes a strange bug in QEMU where it triggers the DEBUG breakpoint handler on unaligned 16-bit stores in the first 4KiB of memory. Aligned stores and store outside of the first 4KiB do not dispatch the DEBUG breakpoint handler. Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/endian.h 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85855/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1 Gerrit-Change-Number: 85855 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: commonlib/include/commonlib: Add volatile qualifier
by Patrick Rudolph (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85855?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: commonlib/include/commonlib: Add volatile qualifier ...................................................................... commonlib/include/commonlib: Add volatile qualifier With the introduction of the stack canary breakpoint QEMU uncovered a different bug within coreboot. Currently the compiler optimizes over aggressively inline functions and memory stores. That also affects write_at_ble8(), which is supposed to store a single byte at time. The compiler however optimizes multiple byte stores into a single wider (and possibly unaligned) store operation. This can be seen in the emited assembly code of write_le16(), as used to install the EBDA: 401348a: 66 c7 04 25 13 04 00 movw $0x400,0x413 4013491: 00 00 04 Make sure that the compiler does not optimize multiple calls to write_at_ble8() by adding the volatile qualifier. The emitted assembly code of the same function changes to: 401394c: c6 04 25 13 04 00 00 movb $0x0,0x413 4013953: 00 4013954: c6 04 25 14 04 00 00 movb $0x4,0x414 401395b: 04 Fixes a strange bug in QEMU where it triggers the DEBUG breakpoint handler on unaligned 16-bit stores in the first 4KiB of memory. Aligned stores and store outside of the first 4KiB do not dispatch the DEBUG breakpoint handler. Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/endian.h 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85855/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1 Gerrit-Change-Number: 85855 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit January 2025