coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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3270 discussions

[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable
by Yu-Ping Wu (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86159/comment/4e10b6ab_728f6cdc?us… : PS4, Line 7: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable It's MTK common code, not just 8196. File src/soc/mediatek/common/mmu_operations.c: https://review.coreboot.org/c/coreboot/+/86159/comment/2ad8da93_f43c6b2e?us… : PS4, Line 39: /* mtk_soc_mcufw_reserved set mcufw_reserved to non-cacheable */ No such "mtk_soc*" function. -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 00:18:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add pi_img loader in ramstage
by Yidi Lin (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86161?usp=email ) Change subject: soc/mediatek/mt8196: Add pi_img loader in ramstage ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Gerrit-Change-Number: 86161 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 23:32:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable
by Yidi Lin (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) Change subject: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 23:31:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: tree: Use the default standard for C
by Elyes Haouas (Code Review) 26 Jan '25

26 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86162?usp=email ) Change subject: tree: Use the default standard for C ...................................................................... tree: Use the default standard for C GCC-14 and Clang-18.1.8 uses std=gnu17 by default. The default will be gnu23 for next GCC and Clang versions. Change-Id: I250700f989c033fcb63550218c7af8bbfaf01247 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/libpayload/Makefile M payloads/libpayload/tests/Makefile.mk M tests/Makefile.common M util/cbfstool/Makefile.mk 5 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86162/1 diff --git a/Makefile.mk b/Makefile.mk index bc547de..de195bd 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -507,7 +507,6 @@ CFLAGS_common += -pipe CFLAGS_common += -g CFLAGS_common += -nostdinc -CFLAGS_common += -std=gnu11 CFLAGS_common += -nostdlib CFLAGS_common += -Wall CFLAGS_common += -Wundef diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index afe38dc..cdeacf3 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -216,7 +216,7 @@ AR := $(AR_$(ARCH-y)) endif -CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y)) +CFLAGS += $(CFLAGS_$(ARCH-y)) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index a6cee5f..4194d8b 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -48,7 +48,7 @@ TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type -TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -ffunction-sections -fdata-sections -fno-builtin ifneq ($(filter-out 0,$(DEBUG)),) TEST_CFLAGS += -Og -ggdb3 diff --git a/tests/Makefile.common b/tests/Makefile.common index dd7cca2..70a368e 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -51,7 +51,7 @@ TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs TEST_CFLAGS += -Wno-unused-but-set-variables -TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -ffunction-sections -fdata-sections -fno-builtin ifneq ($(filter-out 0,$(DEBUG)),) TEST_CFLAGS += -Og -ggdb3 diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk index 8577874..6b4df1d 100644 --- a/util/cbfstool/Makefile.mk +++ b/util/cbfstool/Makefile.mk @@ -140,7 +140,6 @@ TOOLCFLAGS += -mno-ms-bitfields endif ifeq ($(shell uname -o 2>/dev/null), Cygwin) -TOOLCFLAGS+=-std=gnu11 TOOLCPPFLAGS+=-D_GNU_SOURCE else TOOLCFLAGS+=-std=c11 -- To view, visit https://review.coreboot.org/c/coreboot/+/86162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I250700f989c033fcb63550218c7af8bbfaf01247 Gerrit-Change-Number: 86162 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85161?usp=email ) Change subject: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: FYI, this breaks a ton of devices which use the default GPE routing, which previously worked fine but now assert since no routes defined in devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/85161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Gerrit-Change-Number: 85161 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 18:28:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: commonlib: Add new "ESE completed AUnit loading" TS
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85830?usp=email ) Change subject: commonlib: Add new "ESE completed AUnit loading" TS ...................................................................... commonlib: Add new "ESE completed AUnit loading" TS BUG=b:376218080 TEST=Boot to OS, check cbmem -t Change-Id: I7a7fa4d8b6f360d6d688051455e8afc992fc7343 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Jamie Ryu: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d34c8ae..f60e040 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -148,6 +148,7 @@ /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ TS_ME_ROM_START = 990, TS_ISSE_DMU_LOAD_END = 991, + TS_ESE_LOAD_AUNIT_END = 992, /* 1000+ reserved for payloads */ @@ -344,6 +345,7 @@ /* Intel ME continued */ TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), + TS_NAME_DEF(TS_ESE_LOAD_AUNIT_END, 0, "ESE completed AUnit loading"), /* Depthcharge entry timestamp */ TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"), -- To view, visit https://review.coreboot.org/c/coreboot/+/85830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a7fa4d8b6f360d6d688051455e8afc992fc7343 Gerrit-Change-Number: 85830 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/erying/tgl: Drop specifying which timers to use
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Alicja Michalska. Matt DeVillier has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86093?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/erying/tgl: Drop specifying which timers to use ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86093/comment/ac72226b_76b2d5c9?us… : PS2, Line 1: Parent: 9dee482a (mb/google/nissa/var/telith: Configure Acoustic noise mitigation) can we get an explanation why / what the effect of doing so is? -- To view, visit https://review.coreboot.org/c/coreboot/+/86093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e0ac1d289447c292a49111251d321c951078e2 Gerrit-Change-Number: 86093 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 16:58:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common: Add Panther Lake DTT support
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86118?usp=email ) Change subject: soc/intel/common: Add Panther Lake DTT support ...................................................................... soc/intel/common: Add Panther Lake DTT support This commit adds the Panther Lake Intel Dynamic Tuning Technology (Intel DTT) PCI Device ID to the list of supported devices in the ACPI Common Block DTT driver. The Panther Lake Intel DTT PCI ID is defined in document #815002, "Panther Lake U/H Processor - External Design Specification - Volume 1". TEST=The SSDT ACPI table includes the DPTF device definition on fatcat board. Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/dtt/dtt.c 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, approved Bora Guvendik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c882fdc..d17dca4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4854,6 +4854,7 @@ #define PCI_DID_INTEL_ADL_DTT 0x461d #define PCI_DID_INTEL_MTL_DTT 0x7d03 #define PCI_DID_INTEL_RPL_DTT 0xa71d +#define PCI_DID_INTEL_PTL_DTT 0xb01d /* Intel CNVi WiFi/BT device IDs */ #define PCI_DID_INTEL_CML_LP_CNVI_WIFI 0x02f0 diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index 1d70335..8b086e0 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -8,6 +8,7 @@ #include <intelblocks/acpi.h> static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_DTT, PCI_DID_INTEL_RPL_DTT, PCI_DID_INTEL_MTL_DTT, PCI_DID_INTEL_CML_DTT, -- To view, visit https://review.coreboot.org/c/coreboot/+/86118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8 Gerrit-Change-Number: 86118 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update Crashlog config
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85614?usp=email ) Change subject: soc/intel/pantherlake: Update Crashlog config ...................................................................... soc/intel/pantherlake: Update Crashlog config This will configure CpuCrashLogEnable regardless of Tracehub configuration as Crashlog feature does not have a dependency with Tracehub. TEST=Build fatcat and check Crashlog is enabled without enabling Tracehub. Change-Id: I6f37e9f4a1f55ffc576af955c92d4073068eb97a Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85614 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 7d965fd..5b96891 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -249,11 +249,12 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { + m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) return; m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT; - m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); switch (CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT) { case HW_DEBUG_TRACEHUB_ACTIVE: -- To view, visit https://review.coreboot.org/c/coreboot/+/85614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f37e9f4a1f55ffc576af955c92d4073068eb97a Gerrit-Change-Number: 85614 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable PCH Energy Report
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85615?usp=email ) Change subject: mb/google/fatcat: Enable PCH Energy Report ...................................................................... mb/google/fatcat: Enable PCH Energy Report This enables PCH Energy report feature. BUG=b:373915085 TEST=Build fatcat and check UPD-PchPmDisableEnergyReport is configured correctly. Change-Id: Ie318f21cf00a74fd68c86dd39efb5e020e444085 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85615 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index ec87353..92ea38d 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -39,12 +39,14 @@ # DPTF enable register "dptf_enable" = "true" - # TODO: Safe Setting. Needs to be removed later # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state auto-demotion register "disable_package_c_state_demotion" = "true" + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "true" + # Enable CNVi BT register "cnvi_bt_core" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/85615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie318f21cf00a74fd68c86dd39efb5e020e444085 Gerrit-Change-Number: 85615 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit January 2025