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Hello Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85654?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
soc/mediatek/mt8196: Add GPUEB support
GPUEB is a micro-processor used for GPU power management. It is also
responsible for controlling GPU DVFS and GPU thermal throttling. This
gpueb load flow adds 47ms to the boot time.
coreboot log:
CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374
Loaded (and reset) gpueb_fw.img in 47 msecs.
TEST=Boot ok
BUG=b:317009620
Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com>
Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2
---
M src/soc/mediatek/common/include/soc/symbols.h
M src/soc/mediatek/mt8196/Kconfig
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/gpueb.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/gpueb.h
A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h
M src/soc/mediatek/mt8196/include/soc/memlayout.ld
M src/soc/mediatek/mt8196/soc.c
9 files changed, 608 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/8
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Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0
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Patch Set 6: Verified+1
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 7: Code-Review+2
(2 comments)
File src/soc/mediatek/mt8196/gpueb.c:
https://review.coreboot.org/c/coreboot/+/85654/comment/ee1c5d50_60abfa6a?us… :
PS7, Line 204: Failed to parse load buffer
Buffer size too small
https://review.coreboot.org/c/coreboot/+/85654/comment/65dff507_ebd8f260?us… :
PS7, Line 233: {
remove
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Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Helllo @shuo.liu@intel.com; thanks for having looked at the patch. […]
Hi Ariel, LGTM and please check with others.
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Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/ebg/soc_xhci.c:
https://review.coreboot.org/c/coreboot/+/85809/comment/ef3aef40_44ceb28d?us… :
PS3, Line 21:
When get_xhci_bar is called, the initial mapping is assumed to be mapped by FSP and not coreboot here, right?
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Change subject: mb/google/rauru: Initialize clkbuf and srclken in romstage
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Make use of PCI driver for xHCI
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Maybe add a comment to indicate it will be called at src/soc/intel/common/block/xhci/xhci.c?
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