coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/starlabs/{byte_adl,starlite_adl}: Add SSD detect timeout
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86150?usp=email ) Change subject: mb/starlabs/{byte_adl,starlite_adl}: Add SSD detect timeout ...................................................................... mb/starlabs/{byte_adl,starlite_adl}: Add SSD detect timeout It seems that this is needed for specific drives, specifically, the WD Black SN770. Change-Id: Ibade3043489b82e5308231472dfe2c629b591661 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86150 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 50ea3ba..6ba3e7d 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -180,6 +180,7 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L0S_L1, .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, }" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 3174a81..16603f3 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -156,6 +156,7 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L0S_L1, .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, }" smbios_slot_desc "SlotTypeM2Socket3" -- To view, visit https://review.coreboot.org/c/coreboot/+/86150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibade3043489b82e5308231472dfe2c629b591661 Gerrit-Change-Number: 86150 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Revert "mb/starlabs/starbook/adl_n: Remove SSD detect delay"
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86149?usp=email ) Change subject: Revert "mb/starlabs/starbook/adl_n: Remove SSD detect delay" ...................................................................... Revert "mb/starlabs/starbook/adl_n: Remove SSD detect delay" This reverts commit b3718dee9ce703456d8c31e82938d1a886de9873. It seems that this is needed for specific drives, specifically, the WD Black SN770. Change-Id: I5ac2ea7978fca455d39fc7663e5cb219f3f8746f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86149 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index 8342993..d9892c5 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -187,6 +187,7 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L0S_L1, .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, }" smbios_slot_desc "SlotTypeM2Socket3" -- To view, visit https://review.coreboot.org/c/coreboot/+/86149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ac2ea7978fca455d39fc7663e5cb219f3f8746f Gerrit-Change-Number: 86149 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Drop PNP definition for 4e.00
by Matt DeVillier (Code Review) 26 Jan '25

26 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86147?usp=email ) Change subject: mb/starlabs/*: Drop PNP definition for 4e.00 ...................................................................... mb/starlabs/*: Drop PNP definition for 4e.00 There are no resources to allocate for LDN 0, so drop it to eliminate a spurious cbmem log error (PNP 4e.00: missing read resources). Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86147 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 12 files changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 3443726..50ea3ba 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -205,7 +205,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index 629668e..46aedd1 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -107,7 +107,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 549c022..c906dbb 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -107,7 +107,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.04 off end # System Wake-Up device pnp 4e.05 off end # Mouse device pnp 4e.06 on # Keyboard diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 8e1b498..9c19348 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -210,7 +210,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index 2bfe475..8342993 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -217,7 +217,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 9593054..efabe95 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -172,7 +172,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index f50e35d..a9e85ce 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -112,7 +112,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index fa56ef8..c02b642 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -214,7 +214,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 613854f..cc31831 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -221,7 +221,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 7acd36a..938a18f 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -224,7 +224,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index 69d4022..5dfba49 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -253,7 +253,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index cca6059..3174a81 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -182,7 +182,6 @@ chip ec/starlabs/merlin # Port pair 4Eh/4Fh - device pnp 4e.00 on end # IO Interface device pnp 4e.01 off end # Com 1 device pnp 4e.02 off end # Com 2 device pnp 4e.04 off end # System Wake-Up -- To view, visit https://review.coreboot.org/c/coreboot/+/86147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769 Gerrit-Change-Number: 86147 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/i2c: Add NCT3933U Current DAC driver
by Riku Viitanen (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Angel Pons. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85887?usp=email ) Change subject: drivers/i2c: Add NCT3933U Current DAC driver ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebac8065e0b14d85ca0fa9a95f85c834d60d0da2 Gerrit-Change-Number: 85887 Gerrit-PatchSet: 10 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 16:39:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Jayvik Desai (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Jamie Ryu, Kapil Porwal, Pranava Y N. Jayvik Desai has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) Change subject: mb/google/fatcat: Enable s0ix ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 16:36:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) Change subject: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable ...................................................................... Patch Set 4: (5 comments) Patchset: PS1: > Also remove https://review.coreboot.org/c/coreboot/+/86041/5/src/soc/mediatek/mt8196/dv…. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/86159/comment/d2e7fbac_b91ed84d?us… : PS1, Line 7: > mcufw_reserved region Done File src/soc/mediatek/common/mmu_operations.c: https://review.coreboot.org/c/coreboot/+/86159/comment/86d1d5a3_0ad2de8c?us… : PS1, Line 48: mtk_soc_mcufw_reserved(); > MT8173/MT8183/MT8186 do not have this region. […] Done File src/soc/mediatek/mt8196/mmu_cmops.c: https://review.coreboot.org/c/coreboot/+/86159/comment/3b1371c2_e36e8f22?us… : PS1, Line 6: cachable > cacheable Done https://review.coreboot.org/c/coreboot/+/86159/comment/c88667cc_2b5e11c9?us… : PS1, Line 10: NONSECURE > The original SRAM region (where `mcufw_reserved` belongs) is `SECURE_CACHED_MEM`, so I think we shou […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 16:23:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86159?usp=email to look at the new patch set (#4). Change subject: soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable ...................................................................... soc/mediatek/mt8196: Set mcupm mcufw_reserved region to non-cacheable Set mcufw_reserved region to non-cacheable and remove cache operation in dvfs.c. TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8196/dvfs.c 3 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86159/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86159?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable ...................................................................... soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/common/mmu_operations.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86159/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add pi_img loader in ramstage
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86159?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable ...................................................................... soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/mmu_operations.h M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/common/mmu_operations.c 3 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86159/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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