coreboot-gerrit January 2025

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add pi_img loader in ramstage
by Yu-Ping Wu (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86161?usp=email ) Change subject: soc/mediatek/mt8196: Add pi_img loader in ramstage ...................................................................... Patch Set 1: (6 comments) File src/soc/mediatek/mt8196/Kconfig: https://review.coreboot.org/c/coreboot/+/86161/comment/743c48ac_220a631d?us… : PS1, Line 66: config PI_IMG_FIRMWARE sort File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/86161/comment/ec0d149a_f4cd0063?us… : PS1, Line 103: $(CONFIG_PI_IMG_FIRMWARE) sort File src/soc/mediatek/mt8196/include/soc/pi_image.h: https://review.coreboot.org/c/coreboot/+/86161/comment/6ed2ed5b_d86acf7e?us… : PS1, Line 9: #define CSRAM_SIZE (16 * KiB) : #define CSRAM_START_ADDR 0x00120000 ``` #define PI_IMAGE_CSRAM <TABS> 0x00120000 #define PI_IMAGE_CSRAM_SIZE <TABS> (16 * KiB) ``` File src/soc/mediatek/mt8196/pi_image.c: https://review.coreboot.org/c/coreboot/+/86161/comment/08f7e005_6ebcabc2?us… : PS1, Line 15: struct mtk_mcu *pi_image_load(void) I'd prefer returning buffer and size directly, without using mtk_mcu. ``` size_t pi_image_load(void **buffer) { *buffer = NULL; ... *buffer = pi_image.load_buffer; return pi_image.run_size; } ``` File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/86161/comment/9f19cd28_7d819fbb?us… : PS1, Line 40: struct mtk_mcu *pi = pi_image_load(); : : void *pi_image = pi->load_buffer; : size_t pi_image_size = pi->run_size; Following the other comment above, this would be ``` void *pi_image; size_t pi_image_size; pi_image_size = pi_image_load(&pi_image); ``` https://review.coreboot.org/c/coreboot/+/86161/comment/814eb271_3eb91a50?us… : PS1, Line 57: pi_image_prepare How about `add_pi_image_params` -- To view, visit https://review.coreboot.org/c/coreboot/+/86161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Gerrit-Change-Number: 86161 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 15:04:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) Change subject: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/common/mmu_operations.c: https://review.coreboot.org/c/coreboot/+/86159/comment/5f99c1d8_10f16bd4?us… : PS1, Line 48: mtk_soc_mcufw_reserved(); > This region is NOT within DRAM. […] OK, I think it's better to put it in mmu_init. Thank you. File src/soc/mediatek/mt8196/mmu_cmops.c: https://review.coreboot.org/c/coreboot/+/86159/comment/8e18622c_2a15b77f?us… : PS1, Line 10: NONSECURE > I'm not sure, but should this be `SECURE`? I referred to common/mmu_cmops.c, where NONSECURE is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 15:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Update fsp_status enum type
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86160?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/common: Update fsp_status enum type ...................................................................... soc/mediatek/common: Update fsp_status enum type Sync the enum values from mtk-fsp private repo. TEST=build pass. BUG=b:373797027 Change-Id: I8a1cb107f1ff8a65962997e861e8e670cd9582a2 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/mtk_fsp_common.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/86160/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a1cb107f1ff8a65962997e861e8e670cd9582a2 Gerrit-Change-Number: 86160 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Update fsp_status enum type
by Yu-Ping Wu (Code Review) 26 Jan '25

26 Jan '25

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable
by Yu-Ping Wu (Code Review) 26 Jan '25

26 Jan '25

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Add pi_img loader in ramstage
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86161?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Add pi_img loader in ramstage ...................................................................... soc/mediatek/mt8196: Add pi_img loader in ramstage This patch includes loading pi_img through CBFS and passing parameters of pi_img to mtk_fsp for parsing. BUG=b:373797027 TEST=Build pass. boot ok. Locd pi_img with following logs: CBFS: Found 'pi_img.img' @0xb2340 size 0x9620 in mcache @0xfffdd440 read SPI 0x4b43a0 0x9620: 2946 us, 13045 KB/s, 104.360 Mbps VB2:vb2_digest_init() 38432 bytes, hash algo 2, HW acceleration enabled mtk_init_mcu: Loaded (and reset) pi_img.img in 3 msecs (180421 bytes) Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/mtk_fsp_common.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/pi_image.h A src/soc/mediatek/mt8196/pi_image.c M src/soc/mediatek/mt8196/soc.c 6 files changed, 69 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/86161/1 diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h index 29e7ed9..bc0d92c 100644 --- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -16,6 +16,7 @@ FSP_STATUS_PARAM_NOT_FOUND, FSP_STATUS_PARAM_INVALID_SIZE, FSP_STATUS_INVALID_STORAGE, + FSP_STATUS_INVALID_PI_IMG, }; enum fsp_phase { @@ -38,6 +39,8 @@ /* 0x40000000+ reserved for input type params */ FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), FSP_PARAM_TYPE_STORAGE, + FSP_PARAM_TYPE_PI_IMG, + FSP_PARAM_TYPE_PI_IMG_CSRAM, /* 0x80000000+ reserved for output type params */ FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index fe89288..cad1baf 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -63,4 +63,11 @@ help The file name of the MediaTek MCUPM firmware. +config PI_IMG_FIRMWARE + string + default "pi_img.img" + help + The file name of the MediaTek PI_IMG firmware. The main purpose of the pi_img is to + pass various frequency and voltage scaling parameters and settings to MCUPM. + endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index cacb7da..d68317a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -75,6 +75,7 @@ ramstage-y += mt6685_rtc.c ramstage-y += mtcmos.c ramstage-y += ../common/mtk_fsp.c +ramstage-y += pi_image.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c sspm_sram.c @@ -98,7 +99,8 @@ $(CONFIG_GPUEB_FIRMWARE) \ $(CONFIG_MCUPM_FIRMWARE) \ $(CONFIG_SSPM_FIRMWARE) \ - $(CONFIG_SPM_FIRMWARE) + $(CONFIG_SPM_FIRMWARE) \ + $(CONFIG_PI_IMG_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/include/soc/pi_image.h b/src/soc/mediatek/mt8196/include/soc/pi_image.h new file mode 100644 index 0000000..0c0d4c5 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/pi_image.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ +#define __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ + +#include <commonlib/bsd/helpers.h> +#include <soc/mcu_common.h> + +#define CSRAM_SIZE (16 * KiB) +#define CSRAM_START_ADDR 0x00120000 + +struct mtk_mcu *pi_image_load(void); +void pi_image_finalize(void); + +#endif /* __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ */ diff --git a/src/soc/mediatek/mt8196/pi_image.c b/src/soc/mediatek/mt8196/pi_image.c new file mode 100644 index 0000000..84374f3 --- /dev/null +++ b/src/soc/mediatek/mt8196/pi_image.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <arch/cache.h> +#include <assert.h> +#include <soc/mcu_common.h> +#include <soc/pi_image.h> +#include <soc/symbols.h> +#include <string.h> +#include <sys/types.h> + +static struct mtk_mcu pi_image = { + .firmware_name = CONFIG_PI_IMG_FIRMWARE +}; + +struct mtk_mcu *pi_image_load(void) +{ + pi_image.load_buffer = _dram_dma; + pi_image.buffer_size = REGION_SIZE(dram_dma); + + if (mtk_init_mcu(&pi_image)) + die("%s() failed\n", __func__); + + return &pi_image; +} diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 8aca958..17e547e 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -11,6 +11,7 @@ #include <soc/mt6685.h> #include <soc/mtk_fsp.h> #include <soc/pcie.h> +#include <soc/pi_image.h> #include <soc/sspm.h> #include <soc/storage.h> #include <soc/symbols.h> @@ -34,11 +35,26 @@ ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); } +static void pi_image_prepare(void) +{ + struct mtk_mcu *pi = pi_image_load(); + + void *pi_image = pi->load_buffer; + size_t pi_image_size = pi->run_size; + void *csram = (void *)CSRAM_START_ADDR; + size_t csram_size = CSRAM_SIZE; + + mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG, pi_image_size, pi_image); + mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG_CSRAM, csram_size, csram); +} + static void soc_init(struct device *dev) { - mtk_fsp_init(RAMSTAGE_SOC_INIT); uint32_t storage_type = mainboard_get_storage_type(); + + mtk_fsp_init(RAMSTAGE_SOC_INIT); mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type); + pi_image_prepare(); mtk_fsp_load_and_run(); mtk_mmu_disable_l2c_sram(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Gerrit-Change-Number: 86161 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Update fsp_status enum type
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable
by Jarried Lin (Code Review) 26 Jan '25

26 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) Change subject: soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable ...................................................................... soc/mediatek/mt8196: Set mcupm reserved sram to non-cacheable TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/mmu_operations.h M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mmu_cmops.c 4 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86159/1 diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index 9c69447..7721e05 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -18,6 +18,7 @@ void mtk_soc_after_dram(void); void mtk_soc_disable_l2c_sram(void); +void mtk_soc_mcufw_reserved(void); void mtk_mmu_init(void); void mtk_mmu_after_dram(void); diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index be216f6..32ebea0 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -6,6 +6,7 @@ #include <soc/mmu_operations.h> __weak void mtk_soc_after_dram(void) { /* do nothing */ } +__weak void mtk_soc_mcufw_reserved(void) { /* do nothing */ } void mtk_mmu_init(void) { @@ -44,6 +45,7 @@ mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM); mtk_soc_after_dram(); + mtk_soc_mcufw_reserved(); } void mtk_mmu_disable_l2c_sram(void) diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 4cf1660..cacb7da 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -37,7 +37,7 @@ romstage-y += modem_power_ctrl.c romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c mmu_cmops.c romstage-y += ../common/mt6316.c mt6316.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c diff --git a/src/soc/mediatek/mt8196/mmu_cmops.c b/src/soc/mediatek/mt8196/mmu_cmops.c new file mode 100644 index 0000000..8de470f --- /dev/null +++ b/src/soc/mediatek/mt8196/mmu_cmops.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/symbols.h> +#include <soc/mmu_operations.h> + +/* mtk_soc_mcufw_reserved set mcufw_reserved to non-cachable */ +void mtk_soc_mcufw_reserved(void) +{ + mmu_config_range(_mcufw_reserved, REGION_SIZE(mcufw_reserved), + NONSECURE_UNCACHED_MEM); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: mb/google/geralt: Enable CSOT_PNA957QT1_1 panel for Ciri
by Xinxiong Xu (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xinxiong Xu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/86158?usp=email ) Change subject: mb/google/geralt: Enable CSOT_PNA957QT1_1 panel for Ciri ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I306298c6eb172e4dd199e45a50e197fa87905e8c Gerrit-Change-Number: 86158 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 12:59:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/mipi: Add support for CSOT_PNA957QT1_1 panel
by Xinxiong Xu (Code Review) 26 Jan '25

26 Jan '25

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xinxiong Xu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/86157?usp=email ) Change subject: drivers/mipi: Add support for CSOT_PNA957QT1_1 panel ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86157?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd092fa8f2e33f2692c61a7f302224c01678db05 Gerrit-Change-Number: 86157 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 26 Jan 2025 12:58:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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