coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
830 discussions

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... Patch Set 1: (28 comments) File src/soc/mediatek/mt8196/include/soc/srclken_rc.h: https://review.coreboot.org/c/coreboot/+/85842/comment/961cd70d_a154723c?us… : PS1, Line 16: = 5 Remove these. https://review.coreboot.org/c/coreboot/+/85842/comment/c5995b41_2bb455f3?us… : PS1, Line 126: _M What do `_M` and `_B` mean here? If that means MASK, and we remove `_M` and `_MSK_B`? https://review.coreboot.org/c/coreboot/+/85842/comment/7de474e3_810b034d?us… : PS1, Line 184: struct mtk_rc_status_regs { Merge this into the `mtk_rc_regs` struct. Remove `RC_STATE_BASE`. https://review.coreboot.org/c/coreboot/+/85842/comment/eb439e7e_552fdaf7?us… : PS1, Line 202: Remove 2 tabs File src/soc/mediatek/mt8196/srclken_rc.c: https://review.coreboot.org/c/coreboot/+/85842/comment/99ef6135_45dfb346?us… : PS1, Line 32: ~= spaces around `~=` https://review.coreboot.org/c/coreboot/+/85842/comment/7b066acc_361f2a04?us… : PS1, Line 135: Remove extra blank line. https://review.coreboot.org/c/coreboot/+/85842/comment/366496ff_73764c68?us… : PS1, Line 167: #define CHN_MASK (BIT(CHN_DCXO_L) | BIT(CHN_DCXO_H)) : #define CHN_NOT_SUPPORT(i) (BIT(i) & CHN_MASK) For `CHN_NOT_SUPPORT`, `INIT_SUBSYS_FPM2LPM` and `INIT_SUBSYS_TO_HW`, can we change them to an configuration array? ``` static const struct { bool disabled; bool lpm; bool hw_mode; } rc_config[MAX_CHN_NUM] = { [CHN_SUSPEND] = ..., ... [CHN_GPS] = { .lpm = true, .hw_mode = true }, ... [CHN_DCXO_L] = { .disabled = true }, ... }; ``` Alternatively, we can change them to 3 functions: `chn_supported()`, `chn_is_lpm()`, `chn_is_hw_mode()`. https://review.coreboot.org/c/coreboot/+/85842/comment/a3ead1ac_2c0e7acb?us… : PS1, Line 182: * space https://review.coreboot.org/c/coreboot/+/85842/comment/0844bc36_2697c832?us… : PS1, Line 203: XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN `XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN` can be moved to the `SUB_CTRL_CON_UNUSE` macro definition. https://review.coreboot.org/c/coreboot/+/85842/comment/73eba65c_d2c562ec?us… : PS1, Line 225: RG What does RG mean? https://review.coreboot.org/c/coreboot/+/85842/comment/30ca540f_9a3ada71?us… : PS1, Line 265: code flow ASSERT already What does this mean? https://review.coreboot.org/c/coreboot/+/85842/comment/e662b25b_3472fd44?us… : PS1, Line 273: ASSERT assert Same below. https://review.coreboot.org/c/coreboot/+/85842/comment/d598e4fa_bdb64af2?us… : PS1, Line 276: INIT_MODE Can we split `INIT_MODE` to a separate function `rc_ctrl_mode_init`? Then `INIT_MODE` enum value can also be removed. https://review.coreboot.org/c/coreboot/+/85842/comment/aca14355_9bad0d88?us… : PS1, Line 278: rc_ctrl[id] Use a local variable (const pointer) for `rc_ctrl[id]`. https://review.coreboot.org/c/coreboot/+/85842/comment/421c63b7_5bbbd07a?us… : PS1, Line 312: else : return; > ``` […] ``` assert(mode == SW_FPM_HIGH || mode == SW_FPM_LOW); int fpm = SW_FPM_HIGH ? 1 : 0; SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, fpm); ``` https://review.coreboot.org/c/coreboot/+/85842/comment/c194ee59_ef16db2b?us… : PS1, Line 315: rc_ctrl[id].sw_fpm = mode; Can we change `rc_ctrl` const and NOT modify it here? In line #511, we can still get the current fpm value by: ``` unsigned int fpm = rc_ctrl[ch].sw_fpm; if (rc_config[ch].lpm) fpm = SW_FPM_LOW; ``` https://review.coreboot.org/c/coreboot/+/85842/comment/216d58b2_f7bce42b?us… : PS1, Line 346: rc_ctrl_mode_switch_init Adjust the order of these 3 functions: rc_ctrl_mode_switch_init -> rc_init_subsys_lpm -> rc_init_subsys_hw_mode. https://review.coreboot.org/c/coreboot/+/85842/comment/9f5ed530_e5fa57e2?us… : PS1, Line 357: unsigned int state `u32 mask, u32 value` Pass `mask` (0xA) from the caller. https://review.coreboot.org/c/coreboot/+/85842/comment/4378527e_dae01ed0?us… : PS1, Line 357: unsigned int chn `enum chn_id id` https://review.coreboot.org/c/coreboot/+/85842/comment/ec6f4ca8_f765f438?us… : PS1, Line 360: INFO ERROR https://review.coreboot.org/c/coreboot/+/85842/comment/62a784c7_8a4ca796?us… : PS1, Line 378: e E https://review.coreboot.org/c/coreboot/+/85842/comment/42dee60b_072b1dc7?us… : PS1, Line 385: dsb > coreboot read/write APIs already include `dmb()`. […] I have the same question. https://review.coreboot.org/c/coreboot/+/85842/comment/bd517e6d_21d864b3?us… : PS1, Line 401: e E https://review.coreboot.org/c/coreboot/+/85842/comment/1f12f5dd_2ff63a8a?us… : PS1, Line 414: _BF_VALUE `_BF_VALUE` isn't part of the API, so it should never be used. Please use `WRITE32_BITFIELDS`. https://review.coreboot.org/c/coreboot/+/85842/comment/1325ab0a_dd6f3563?us… : PS1, Line 477: u U https://review.coreboot.org/c/coreboot/+/85842/comment/cc48333e_bd1caf13?us… : PS1, Line 514: ret Should return -1 at the end of function if one of the channel fails. Right now we store the return value of the *last* channel, which is wrong. https://review.coreboot.org/c/coreboot/+/85842/comment/50f91f98_46dcac2f?us… : PS1, Line 515: ASSERT(!ret); We shouldn't use assertions for run-time errors. When this fails, should we continue to boot or not? 1. If so, then return -1 here. 2. If not, call `die("...")`. https://review.coreboot.org/c/coreboot/+/85842/comment/57f7b5f3_a8d7f73e?us… : PS1, Line 537: w W -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:35:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Naveen M (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Mac Chiang, Pranava Y N, Weimin Wu. Naveen M has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85571/comment/6be345a3_2c56139e?us… : PS2, Line 13: static struct soundwire_multilane alc711_multilane = { : }; > @Naveen , can you please help here ? understanding the original query from subrata, since there is a struct alc711_multilane defined, whether config->multilane.lane_mapping default values can be made so that when chip detection fails, it will fallback to those default values. Actually default should always be SINGLE_LANE, if kernel doesn't get the configurations for "mipi-sdw-lane-%d-mapping" properties. per soundwire driver team recommendation, there shouldn't be any default values for multi-lane, as it depends on the H/W design. -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com> Comment-In-Reply-To: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85859?usp=email to look at the new patch set (#3). Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8186/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 13 files changed, 84 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Enable x86_64
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Morgan Jang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email ) Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Gerrit-Change-Number: 85805 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 05:43:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85859?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 12 files changed, 76 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85861?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c ...................................................................... soc/mediatek/common/dp: Move common functions to dptx_hal_common.c Move the functions that can be shared with MT8196 to dptx_hal_common.c. The exsisting DP_WRITE1BYTE is used for the bit operation with the mask 0xFF. Adding a new macro DP_CLRSETBITS for the bit operation whose mask is not 0xFF. This macros is prepared for MT8196 because its underly API for DP_WRITE1BYTE and DP_CLRSETBITS is not mtk_dp_write_byte. Therefore, this patch also replaces mtk_dp_write_byte with DP_CLRSETBITS. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_hal.c A src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8188/include/soc/dptx_hal.h M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/dptx_hal.h 7 files changed, 517 insertions(+), 506 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85861/1 diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index c46f457..8ae469e 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -9,8 +9,6 @@ #include <soc/dptx_reg.h> #include <types.h> -#define REG_OFFSET_LIMIT 0x8000 - struct shift_mask { u32 shift; u32 mask; @@ -28,76 +26,6 @@ [DPTX_LANE3] = { DP_TX3_PRE_EMPH_FLDMASK_POS, DP_TX3_PRE_EMPH_FLDMASK }, }; -u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return 0; - } - - return read32(addr); -} - -void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return; - } - - write32(addr, val); -} - -void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return; - } - - /* - * TODO: modify to clrsetbits32(addr, mask, val); - * There is asserion error when testing assert((val & mask) == val). - */ - clrsetbits32(addr, mask, val & mask); -} - -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) -{ - if (addr % 2) { - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); - mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8); - } else { - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x11); - mtk_dp_mask(mtk_dp, addr, val, mask); - } - - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); -} - -void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) -{ - u32 m, n, ls_clk, pix_clk; - - m = mtk_dp_read(mtk_dp, REG_33C8_DP_ENCODER1_P0); - n = 0x8000; - ls_clk = mtk_dp->train_info.linkrate; - ls_clk *= 27; - - pix_clk = m * ls_clk / n; - printk(BIOS_DEBUG, "DPTX calc pixel clock = %d MHz, dp_intf clock = %dMHz\n", - pix_clk, pix_clk / 4); -} - void dptx_hal_init_setting(struct mtk_dp *mtk_dp) { DP_WRITE1BYTE(mtk_dp, REG_342C_DP_TRANS_P0, 0x69); @@ -107,12 +35,6 @@ mtk_dp_mask(mtk_dp, DP_TX_TOP_IRQ_MASK, BIT(2), BIT(2)); } -void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) -{ - mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, - enable ? 0 : 0x3ff, 0x3ff); -} - void dptx_hal_set_msa(struct mtk_dp *mtk_dp) { u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal; @@ -193,154 +115,16 @@ } } -void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) -{ - u8 val; - - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, - color_depth << 0x5, 0xe0); - - switch (color_depth) { - case DP_COLOR_DEPTH_6BIT: - val = 4; - break; - case DP_COLOR_DEPTH_8BIT: - val = 3; - break; - case DP_COLOR_DEPTH_10BIT: - val = 2; - break; - case DP_COLOR_DEPTH_12BIT: - val = 1; - break; - case DP_COLOR_DEPTH_16BIT: - val = 0; - break; - default: - return; - } - mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); -} - -void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]) -{ - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe); - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff); -} - -void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, - bool enable, u32 video_m, u32 video_n) -{ - if (enable) { - /* Turn on overwrite MN */ - DP_WRITE2BYTE(mtk_dp, REG_3008_DP_ENCODER0_P0, - video_m & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_300C_DP_ENCODER0_P0, - (video_m >> 16) & 0xff); - DP_WRITE2BYTE(mtk_dp, REG_3044_DP_ENCODER0_P0, - video_n & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_3048_DP_ENCODER0_P0, - (video_n >> 16) & 0xff); - DP_WRITE2BYTE(mtk_dp, REG_3050_DP_ENCODER0_P0, - video_n & 0xffff); - - /* Add legerII. */ - DP_WRITE1BYTE(mtk_dp, REG_3054_DP_ENCODER0_P0, - (video_n >> 16) & 0xff); - mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, - BIT(0), BIT(0)); - } else { - /* Turn off overwrite MN */ - mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, - 0, BIT(0)); - } -} - -u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) -{ - u8 color_bpp; - u8 color_depth = mtk_dp->info.depth; - u8 color_format = mtk_dp->info.format; - - switch (color_depth) { - case DP_COLOR_DEPTH_6BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 16; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 12; - else - color_bpp = 18; - break; - case DP_COLOR_DEPTH_8BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 16; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 12; - else - color_bpp = 24; - break; - case DP_COLOR_DEPTH_10BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 20; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 15; - else - color_bpp = 30; - break; - case DP_COLOR_DEPTH_12BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 24; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 18; - else - color_bpp = 36; - break; - case DP_COLOR_DEPTH_16BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 32; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 24; - else - color_bpp = 48; - break; - default: - color_bpp = 24; - printk(BIOS_ERR, "Set wrong bpp = %d\n", color_bpp); - break; - } - - return color_bpp; -} - -void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) -{ - /* - * [5:0] video sram start address - * modify in 480P case only, default=0x1f - */ - mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f); -} - -void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) -{ - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); -} - -void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) -{ - mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); -} - void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) { - mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, - BIT(7), BIT(7)); + DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, + BIT(7), BIT(7)); DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020); mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020, 0xfff); - mtk_dp_write_byte(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1, - 0x2, BIT(1) | BIT(0)); - mtk_dp_write_byte(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1, - 0x40, 0x70); + DP_CLRSETBITS(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1, + 0x2, BIT(1) | BIT(0)); + DP_CLRSETBITS(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1, + 0x40, 0x70); DP_WRITE2BYTE(mtk_dp, REG_3368_DP_ENCODER1_P0, 0x1111); } @@ -349,211 +133,6 @@ return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2); } -bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *rx_buf) -{ - bool valid_cmd = false; - u8 reply_cmd, aux_irq_status; - int rd_count; - u32 wait_reply_count = AUX_WAITREPLY_LPNUM; - - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - mdelay(1); - - if (length > 16 || (cmd == AUX_CMD_NATIVE_R && length == 0x0)) - return false; - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); - DP_WRITE2BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf); - - if (length > 0) { - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - (length - 1) << MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS, - MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - } - - if (cmd == AUX_CMD_I2C_R || cmd == AUX_CMD_I2C_R_MOT0) - if (length == 0x0) - mtk_dp_mask(mtk_dp, REG_362C_AUX_TX_P0, - 0x1 << AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS, - AUX_NO_LENGTH_AUX_TX_P0_FLDMASK); - - mtk_dp_mask(mtk_dp, REG_3630_AUX_TX_P0, - 0x1 << AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS, - AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK); - - while (--wait_reply_count) { - if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & - AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & - AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; - - if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) { - printk(BIOS_ERR, "(AUX Read)HW Timeout 400us irq\n"); - break; - } - } - - reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; - - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); - if (phy_status != 0x1) - printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n"); - - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, - MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n", - wait_reply_count); - return false; - } - - if (length == 0) { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - } else { - if (valid_cmd) { - mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, - 0x0 << AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS, - AUX_RD_MODE_AUX_TX_P0_FLDMASK); - - for (rd_count = 0; rd_count < length; rd_count++) { - mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, - 0x1 << AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS, - AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK); - mdelay(1); - *(rx_buf + rd_count) = mtk_dp_read(mtk_dp, - REG_3620_AUX_TX_P0); - } - } else { - printk(BIOS_INFO, "Read TimeOut %#x\n", dpcd_addr); - } - } - - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, - MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - return valid_cmd; -} - -bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data) -{ - bool valid_cmd = false; - u8 reply_cmd; - int i; - u16 wait_reply_count = AUX_WAITREPLY_LPNUM; - int reg_idx; - - mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, - 1 << AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS, - AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - mdelay(1); - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); - DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xff); - DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0 + 1, - (dpcd_addr >> 8) & 0xff); - DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, - (dpcd_addr >> 16) & 0xf); - - if (length > 0) { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - for (i = 0; i < (length + 1) / 2; i++) - for (reg_idx = 0; reg_idx < 2; reg_idx++) - if ((i * 2 + reg_idx) < length) - DP_WRITE1BYTE(mtk_dp, - REG_3708_AUX_TX_P0 + i * 4 + reg_idx, - data[i * 2 + reg_idx]); - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, - ((length - 1) & 0xf) << 4); - } else { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x1); - } - - mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, - AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK, - AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3630_AUX_TX_P0, 0x8); - - while (--wait_reply_count) { - u8 aux_irq_status; - - aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; - mdelay(1); - if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) - break; - } - - reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; - - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); - if (phy_status != 0x1) - printk(BIOS_ERR, - "Aux write: aux hang, need SW reset!\n"); - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - - printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n", - reply_cmd, wait_reply_count); - return false; - } - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - - if (length == 0) - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - - return valid_cmd; -} - bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, int swing_value, int preemphasis) { @@ -586,13 +165,6 @@ 0, volt_preemphasis[lane].mask); } -void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable) -{ - /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ - mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0, - enable ? 0 : GENMASK(7, 5), GENMASK(7, 5)); -} - void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0, @@ -749,76 +321,8 @@ mtk_dp_write(mtk_dp, 0x2000, 0x3); } -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value) -{ - /* if Set TPS1. */ - if (value == BIT(4)) - dptx_hal_phy_setidlepattern(mtk_dp, false); - - mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1, - value, GENMASK(7, 4)); -} - void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable) { mtk_dp_write_byte(mtk_dp, REG_3580_DP_TRANS_P0 + 1, enable ? 0xf : 0x0, 0xf); } - -void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) -{ - /* - * [4]: REG_enhanced_frame_mode - * [1 : 0]: REG_lane_num - */ - if (enable) - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(4), BIT(4)); - else - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - 0, BIT(4)); -} - -void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) -{ - /* [0]: dp tx transmitter scramble enable. */ - if (enable) - mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, - BIT(0), BIT(0)); - else - mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, - 0, BIT(0)); -} - -void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) -{ - if (enable) { - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(3) | BIT(2), BIT(3) | BIT(2)); - mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, - BIT(3) | BIT(4), BIT(3) | BIT(4)); - } else { - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(3), BIT(3) | BIT(2)); - mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, - BIT(4), BIT(3) | BIT(4)); - } - printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c)); -} - -void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) -{ - if (enable) { - mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, - 0, BIT(4)); - mdelay(1); - mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, - BIT(4), BIT(4)); - } else { - DP_WRITE2BYTE(mtk_dp, TOP_OFFSET, 0x0); - mdelay(1); - DP_WRITE2BYTE(mtk_dp, 0x0034, 0x4aa); - DP_WRITE2BYTE(mtk_dp, 0x1040, 0x0); - DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555); - } -} diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c new file mode 100644 index 0000000..26030f9 --- /dev/null +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <delay.h> +#include <edid.h> +#include <soc/dptx.h> +#include <soc/dptx_hal.h> +#include <soc/dptx_reg.h> +#include <types.h> + +#define REG_OFFSET_LIMIT 0x8000 + +u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return 0; + } + + return read32(addr); +} +void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return; + } + + write32(addr, val); +} + +void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", + __func__, offset, mtk_dp->regs); + return; + } + + /* + * TODO: modify to clrsetbits32(addr, mask, val); + * There is asserion error when testing assert((val & mask) == val). + */ + clrsetbits32(addr, mask, val & mask); +} + +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) +{ + if (addr % 2) { + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); + mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8); + } else { + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x11); + mtk_dp_mask(mtk_dp, addr, val, mask); + } + + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); +} + +void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) +{ + u32 m, n, ls_clk, pix_clk; + + m = mtk_dp_read(mtk_dp, REG_33C8_DP_ENCODER1_P0); + n = 0x8000; + ls_clk = mtk_dp->train_info.linkrate; + ls_clk *= 27; + + pix_clk = m * ls_clk / n; + printk(BIOS_DEBUG, "DPTX calc pixel clock = %d MHz, dp_intf clock = %dMHz\n", + pix_clk, pix_clk / 4); +} + +void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) +{ + mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, + enable ? 0 : 0x3ff, 0x3ff); +} + +void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) +{ + u8 val; + + DP_CLRSETBITS(mtk_dp, REG_3034_DP_ENCODER0_P0, + color_depth << 0x5, 0xe0); + + switch (color_depth) { + case DP_COLOR_DEPTH_6BIT: + val = 4; + break; + case DP_COLOR_DEPTH_8BIT: + val = 3; + break; + case DP_COLOR_DEPTH_10BIT: + val = 2; + break; + case DP_COLOR_DEPTH_12BIT: + val = 1; + break; + case DP_COLOR_DEPTH_16BIT: + val = 0; + break; + default: + return; + } + DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); +} + +void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]) +{ + DP_CLRSETBITS(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe); + DP_CLRSETBITS(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff); +} + +void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, + bool enable, u32 video_m, u32 video_n) +{ + if (enable) { + /* Turn on overwrite MN */ + DP_WRITE2BYTE(mtk_dp, REG_3008_DP_ENCODER0_P0, + video_m & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_300C_DP_ENCODER0_P0, + (video_m >> 16) & 0xff); + DP_WRITE2BYTE(mtk_dp, REG_3044_DP_ENCODER0_P0, + video_n & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_3048_DP_ENCODER0_P0, + (video_n >> 16) & 0xff); + DP_WRITE2BYTE(mtk_dp, REG_3050_DP_ENCODER0_P0, + video_n & 0xffff); + + /* Add legerII. */ + DP_WRITE1BYTE(mtk_dp, REG_3054_DP_ENCODER0_P0, + (video_n >> 16) & 0xff); + DP_CLRSETBITS(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, + BIT(0), BIT(0)); + } else { + /* Turn off overwrite MN */ + DP_CLRSETBITS(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, + 0, BIT(0)); + } +} + +u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) +{ + u8 color_bpp; + u8 color_depth = mtk_dp->info.depth; + u8 color_format = mtk_dp->info.format; + + switch (color_depth) { + case DP_COLOR_DEPTH_6BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 16; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 12; + else + color_bpp = 18; + break; + case DP_COLOR_DEPTH_8BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 16; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 12; + else + color_bpp = 24; + break; + case DP_COLOR_DEPTH_10BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 20; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 15; + else + color_bpp = 30; + break; + case DP_COLOR_DEPTH_12BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 24; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 18; + else + color_bpp = 36; + break; + case DP_COLOR_DEPTH_16BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 32; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 24; + else + color_bpp = 48; + break; + default: + color_bpp = 24; + printk(BIOS_ERR, "Set wrong bpp = %d\n", color_bpp); + break; + } + + return color_bpp; +} + +void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) +{ + /* + * [5:0] video sram start address + * modify in 480P case only, default=0x1f + */ + DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f); +} + +void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) +{ + mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); +} + +void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) +{ + mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); +} + +bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, + u32 dpcd_addr, size_t length, u8 *rx_buf) +{ + bool valid_cmd = false; + u8 reply_cmd, aux_irq_status; + int rd_count; + u32 wait_reply_count = AUX_WAITREPLY_LPNUM; + + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + mdelay(1); + + if (length > 16 || (cmd == AUX_CMD_NATIVE_R && length == 0x0)) + return false; + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); + DP_WRITE2BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf); + + if (length > 0) { + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + (length - 1) << MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS, + MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + } + + if (cmd == AUX_CMD_I2C_R || cmd == AUX_CMD_I2C_R_MOT0) + if (length == 0x0) + mtk_dp_mask(mtk_dp, REG_362C_AUX_TX_P0, + 0x1 << AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS, + AUX_NO_LENGTH_AUX_TX_P0_FLDMASK); + + mtk_dp_mask(mtk_dp, REG_3630_AUX_TX_P0, + 0x1 << AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS, + AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK); + + while (--wait_reply_count) { + if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & + AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & + AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; + + if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) { + printk(BIOS_ERR, "(AUX Read)HW Timeout 400us irq\n"); + break; + } + } + + reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; + if (reply_cmd) + printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); + + if (wait_reply_count == 0x0 || reply_cmd) { + u8 phy_status = 0x0; + + phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + if (phy_status != 0x1) + printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n"); + + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, + MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n", + wait_reply_count); + return false; + } + + if (length == 0) { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + } else { + if (valid_cmd) { + mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, + 0x0 << AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS, + AUX_RD_MODE_AUX_TX_P0_FLDMASK); + + for (rd_count = 0; rd_count < length; rd_count++) { + mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, + 0x1 << AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS, + AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK); + mdelay(1); + *(rx_buf + rd_count) = mtk_dp_read(mtk_dp, + REG_3620_AUX_TX_P0); + } + } else { + printk(BIOS_INFO, "Read TimeOut %#x\n", dpcd_addr); + } + } + + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, + MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + return valid_cmd; +} + +bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, + u32 dpcd_addr, size_t length, u8 *data) +{ + bool valid_cmd = false; + u8 reply_cmd; + int i; + u16 wait_reply_count = AUX_WAITREPLY_LPNUM; + int reg_idx; + + DP_CLRSETBITS(mtk_dp, REG_3704_AUX_TX_P0, + 1 << AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS, + AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + mdelay(1); + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); + DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xff); + DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0 + 1, + (dpcd_addr >> 8) & 0xff); + DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, + (dpcd_addr >> 16) & 0xf); + + if (length > 0) { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + for (i = 0; i < (length + 1) / 2; i++) + for (reg_idx = 0; reg_idx < 2; reg_idx++) + if ((i * 2 + reg_idx) < length) + DP_WRITE1BYTE(mtk_dp, + REG_3708_AUX_TX_P0 + i * 4 + reg_idx, + data[i * 2 + reg_idx]); + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, + ((length - 1) & 0xf) << 4); + } else { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x1); + } + + DP_CLRSETBITS(mtk_dp, REG_3704_AUX_TX_P0, + AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK, + AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3630_AUX_TX_P0, 0x8); + + while (--wait_reply_count) { + u8 aux_irq_status; + + aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; + mdelay(1); + if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) + break; + } + + reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; + if (reply_cmd) + printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); + + if (wait_reply_count == 0x0 || reply_cmd) { + u8 phy_status = 0x0; + + phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + if (phy_status != 0x1) + printk(BIOS_ERR, + "Aux write: aux hang, need SW reset!\n"); + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + + printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n", + reply_cmd, wait_reply_count); + return false; + } + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + + if (length == 0) + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + + return valid_cmd; +} + +void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable) +{ + /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ + DP_CLRSETBITS(mtk_dp, REG_3418_DP_TRANS_P0, enable ? 0 : GENMASK(7, 5), + GENMASK(7, 5)); +} + +void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value) +{ + /* if Set TPS1. */ + if (value == BIT(4)) + dptx_hal_phy_setidlepattern(mtk_dp, false); + + DP_CLRSETBITS(mtk_dp, REG_3400_DP_TRANS_P0 + 1, value, GENMASK(7, 4)); +} + +void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) +{ + /* + * [4]: REG_enhanced_frame_mode + * [1 : 0]: REG_lane_num + */ + if (enable) + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, + BIT(4), BIT(4)); + else + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, + 0, BIT(4)); +} + +void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) +{ + /* [0]: dp tx transmitter scramble enable. */ + if (enable) + DP_CLRSETBITS(mtk_dp, REG_3404_DP_TRANS_P0, BIT(0), BIT(0)); + else + DP_CLRSETBITS(mtk_dp, REG_3404_DP_TRANS_P0, 0, BIT(0)); +} + +void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) +{ + if (enable) { + DP_CLRSETBITS(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(3) | BIT(2), + BIT(3) | BIT(2)); + DP_CLRSETBITS(mtk_dp, DP_TX_SECURE_REG11, BIT(3) | BIT(4), + BIT(3) | BIT(4)); + } else { + DP_CLRSETBITS(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(3), + BIT(3) | BIT(2)); + DP_CLRSETBITS(mtk_dp, DP_TX_SECURE_REG11, BIT(4), + BIT(3) | BIT(4)); + } + printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c)); +} + +void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) +{ + if (enable) { + DP_CLRSETBITS(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, 0, BIT(4)); + mdelay(1); + DP_CLRSETBITS(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, BIT(4), BIT(4)); + } else { + DP_WRITE2BYTE(mtk_dp, TOP_OFFSET, 0x0); + mdelay(1); + DP_WRITE2BYTE(mtk_dp, 0x0034, 0x4aa); + DP_WRITE2BYTE(mtk_dp, 0x1040, 0x0); + DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555); + } +} diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 778fe46..3a0e892 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -15,8 +15,6 @@ #define DP_AUX_NATIVE_WRITE 0x8 #define DP_AUX_NATIVE_READ 0x9 -#define DP_WRITE1BYTE(mtk_dp, reg, u8_val) \ - mtk_dp_write_byte(mtk_dp, reg, u8_val, 0xff) #define DP_WRITE2BYTE(mtk_dp, reg, u16_val) \ mtk_dp_mask(mtk_dp, reg, u16_val, 0xffff) diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index c09317e..2f1a0f5 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -39,7 +39,7 @@ ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/display.c -ramstage-y += ../common/dp/dptx_common.c +ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h index 4cf1e62..192b3f5 100644 --- a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h +++ b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h @@ -3,4 +3,9 @@ #include <soc/dptx_hal_common.h> +#define DP_CLRSETBITS(mtk_dp, reg, val, mask) \ + mtk_dp_write_byte(mtk_dp, reg, val, mask) +#define DP_WRITE1BYTE(mtk_dp, reg, val) \ + DP_CLRSETBITS(mtk_dp, reg, (val) & 0xFF, 0xFF) + #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 85e261e..7c3d3f4 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -50,7 +50,7 @@ ramstage-y += ../common/display.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c -ramstage-y += ../common/dp/dptx_common.c +ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += emi.c ramstage-y += hdmi.c diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h index 1409310..51bbae6 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h +++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h @@ -2,5 +2,9 @@ #define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ #include <soc/dptx_hal_common.h> +#define DP_CLRSETBITS(mtk_dp, reg, val, mask) \ + mtk_dp_write_byte(mtk_dp, reg, val, mask) +#define DP_WRITE1BYTE(mtk_dp, reg, val) \ + DP_CLRSETBITS(mtk_dp, reg, (val) & 0xFF, 0xFF) #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Gerrit-Change-Number: 85861 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... soc/mediatek/common/dp: Move common functions to dptx_common.c Move the functions that can be shared with MT8196 to dptx_common.c. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx.c A src/soc/mediatek/common/dp/dptx_common.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 5 files changed, 554 insertions(+), 525 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85860/1 diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx.c index c123f88..5f12039 100644 --- a/src/soc/mediatek/common/dp/dptx.c +++ b/src/soc/mediatek/common/dp/dptx.c @@ -12,254 +12,6 @@ #include <soc/dp_intf.h> #include <string.h> -#define ONE_BLOCK_SIZE 128 - -#define DP_LINK_CONSTANT_N_VALUE 0x8000 -#define DP_LINK_STATUS_SIZE 6 - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -#define DP_LANE_CR_DONE (1 << 0) -#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -#define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_BRANCH_OUI_HEADER_SIZE 0xc -#define DP_RECEIVER_CAP_SIZE 0xf -#define DP_DSC_RECEIVER_CAP_SIZE 0xf -#define EDP_PSR_RECEIVER_CAP_SIZE 2 -#define EDP_DISPLAY_CTL_CAP_SIZE 3 -#define DP_LTTPR_COMMON_CAP_SIZE 8 -#define DP_LTTPR_PHY_CAP_SIZE 3 - -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e -#define DP_TRAINING_AUX_RD_MASK 0x7f -#define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) - -#define DP_EDP_DPCD_REV 0x700 -#define DP_EDP_11 0x00 -#define DP_EDP_12 0x01 -#define DP_EDP_13 0x02 -#define DP_EDP_14 0x03 -#define DP_EDP_14a 0x04 -#define DP_EDP_14b 0x05 - -/* Receiver Capability */ -#define DP_DPCD_REV 0x000 -#define DP_DPCD_REV_10 0x10 -#define DP_DPCD_REV_11 0x11 -#define DP_DPCD_REV_12 0x12 -#define DP_DPCD_REV_13 0x13 -#define DP_DPCD_REV_14 0x14 - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) -#define DP_STREAM_REGENERATION_STATUS (1 << 2) - -#define DP_AUX_MAX_PAYLOAD_BYTES 16 - -#define MAX_LANECOUNT 4 - -enum { - DP_LANECOUNT_1 = 0x1, - DP_LANECOUNT_2 = 0x2, - DP_LANECOUNT_4 = 0x4, -}; - -enum { - DP_VERSION_11 = 0x11, - DP_VERSION_12 = 0x12, - DP_VERSION_14 = 0x14, - DP_VERSION_12_14 = 0x16, - DP_VERSION_14_14 = 0x17, - DP_VERSION_MAX, -}; - -enum { - DPTX_SWING0 = 0x00, - DPTX_SWING1 = 0x01, - DPTX_SWING2 = 0x02, - DPTX_SWING3 = 0x03, -}; - -enum { - DPTX_PREEMPHASIS0 = 0x00, - DPTX_PREEMPHASIS1 = 0x01, - DPTX_PREEMPHASIS2 = 0x02, - DPTX_PREEMPHASIS3 = 0x03, -}; - -enum { - DPTX_PASS = 0, - DPTX_PLUG_OUT = 1, - DPTX_TIMEOUT = 2, - DPTX_AUTH_FAIL = 3, - DPTX_EDID_FAIL = 4, - DPTX_TRANING_FAIL = 5, - DPTX_TRANING_STATE_CHANGE = 6, -}; - -enum { - FEC_ERROR_COUNT_DISABLE = 0x0, - FEC_UNCORRECTED_BLOCK_ERROR_COUNT = 0x1, - FEC_CORRECTED_BLOCK_ERROR_COUNT = 0x2, - FEC_BIT_ERROR_COUNT = 0x3, - FEC_PARITY_BLOCK_ERROR_COUNT = 0x4, - FEC_PARITY_BIT_ERROR_COUNT = 0x5, -}; - -enum { - DPTX_NTSTATE_STARTUP = 0x0, - DPTX_NTSTATE_CHECKCAP = 0x1, - DPTX_NTSTATE_CHECKEDID = 0x2, - DPTX_NTSTATE_TRAINING_PRE = 0x3, - DPTX_NTSTATE_TRAINING = 0x4, - DPTX_NTSTATE_CHECKTIMING = 0x5, - DPTX_NTSTATE_NORMAL = 0x6, - DPTX_NTSTATE_POWERSAVE = 0x7, - DPTX_NTSTATE_DPIDLE = 0x8, - DPTX_NTSTATE_MAX, -}; - -enum { - DPTX_DISP_NONE = 0, - DPTX_DISP_RESUME = 1, - DPTX_DISP_SUSPEND = 2, -}; - -enum { - TRAIN_STEP_SUCCESS = 0, - TRAIN_STEP_FAIL_BREAK = 1, - TRAIN_STEP_FAIL_NOT_BREAK = 2, -}; - -#define DPTX_TRAIN_RETRY_LIMIT 0x8 -#define DPTX_TRAIN_MAX_ITERATION 0x5 - -#define HPD_INT_EVNET BIT(3) -#define HPD_CONNECT BIT(2) -#define HPD_DISCONNECT BIT(1) -#define HPD_INITIAL_STATE 0 - -static bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data) -{ - if (retry(7, dptx_hal_auxwrite_bytes(mtk_dp, cmd, dpcd_addr, length, data), - mdelay(1))) - return true; - - printk(BIOS_ERR, "aux write fail: cmd = %d, addr = %#x, len = %ld\n", - cmd, dpcd_addr, length); - - return false; -} - -static bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data) -{ - bool ret = true; - size_t offset = 0; - size_t len; - - while (offset < length) { - len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES); - ret &= dptx_auxwrite_bytes(mtk_dp, cmd, dpcd_addr + offset, - len, data + offset); - offset += len; - } - return ret; -} - -static bool dptx_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data) -{ - if (retry(7, dptx_hal_auxread_bytes(mtk_dp, cmd, dpcd_addr, length, data), - mdelay(1))) - return true; - - printk(BIOS_ERR, "aux read fail: cmd = %d, addr = %#x, len = %ld\n", - cmd, dpcd_addr, length); - - return false; -} - -static bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *rxbuf) -{ - bool ret = true; - size_t offset = 0; - size_t len; - - while (offset < length) { - len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES); - ret &= dptx_auxread_bytes(mtk_dp, cmd, dpcd_addr + offset, - len, rxbuf + offset); - offset += len; - } - return ret; -} - -static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out) -{ - int ret; - u8 edid[ONE_BLOCK_SIZE]; - u8 tmp = 0; - - dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp); - - for (tmp = 0; tmp < ONE_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++) - dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ, - 0x50, DP_AUX_MAX_PAYLOAD_BYTES, - edid + tmp * 16); - - ret = decode_edid(edid, ONE_BLOCK_SIZE, out); - if (ret != EDID_CONFORMANT) { - printk(BIOS_ERR, "failed to decode edid(%d).\n", ret); - return -1; - } - - mtk_dp->edid = out; - return 0; -} - -static u8 dptx_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) -{ - return link_status[r - DP_LANE0_1_STATUS]; -} - -static u8 dptx_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane) -{ - int i = DP_LANE0_1_STATUS + (lane >> 1); - int s = (lane & 1) * 4; - u8 l = dptx_link_status(link_status, i); - - return (l >> s) & 0xf; -} - -static bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane_count) -{ - int lane; - u8 lane_status; - - for (lane = 0; lane < lane_count; lane++) { - lane_status = dptx_get_lane_status(link_status, lane); - if ((lane_status & DP_LANE_CR_DONE) == 0) - return false; - } - return true; -} - static void dptx_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { u32 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & @@ -315,209 +67,6 @@ return true; } -static void dptx_videomute(struct mtk_dp *mtk_dp, bool enable) -{ - dptx_hal_videomute(mtk_dp, enable); -} - -static void dptx_fec_ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel) -{ - u8 i, data[3]; - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, 0x90, 0x1, data); - printk(BIOS_DEBUG, "FEC Capable[0], [0:3] should be 1: %#x\n", - data[0]); - - /* - * FEC error count select 120[3:1]: - * 000b: FEC_ERROR_COUNT_DIS - * 001b: UNCORRECTED_BLOCK_ERROR_COUNT - * 010b: CORRECTED_BLOCK_ERROR_COUNT - * 011b: BIT_ERROR_COUNT - * 100b: PARITY_BLOCK_ERROR_COUNT - * 101b: PARITY_BIT_ERROR_COUNT - */ - if (data[0] & BIT(0)) { - mtk_dp->has_fec = true; - data[0] = (err_cnt_sel << 1) | 0x1; - - dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, - 0x120, 0x1, data); - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - 0x280, 0x3, data); - - for (i = 0; i < 3; i++) - printk(BIOS_DEBUG, "FEC status & error Count: %#x\n", - data[i]); - } -} - -static void dptx_init_variable(struct mtk_dp *mtk_dp) -{ - mtk_dp->regs = (void *)EDP_BASE; - mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3; - mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2; - mtk_dp->train_info.linklane_count = DP_LANECOUNT_4; - mtk_dp->train_info.sink_extcap_en = false; - mtk_dp->train_info.sink_ssc_en = false; - mtk_dp->train_info.tps3 = true; - mtk_dp->train_info.tps4 = true; - mtk_dp->training_state = DPTX_NTSTATE_STARTUP; - mtk_dp->info.format = DP_COLOR_FORMAT_RGB_444; - mtk_dp->info.depth = DP_COLOR_DEPTH_8BIT; - mtk_dp->power_on = false; - mtk_dp->video_enable = false; - mtk_dp->dp_ready = false; - mtk_dp->has_dsc = false; - mtk_dp->has_fec = false; - mtk_dp->dsc_enable = false; -} - -static inline bool dptx_check_res_sample_rate(const struct edid *edid) -{ - return edid->mode.va + edid->mode.vbl <= 525; -} - -static void dptx_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 sram_read_start) -{ - u32 count = 0; /* count: sdp_down_cnt_init */ - u8 offset; - - if (mtk_dp->edid->mode.pixel_clock > 0) - count = (sram_read_start * 2700 * 8 * - mtk_dp->train_info.linkrate) / - (mtk_dp->edid->mode.pixel_clock * 4); - - switch (mtk_dp->train_info.linklane_count) { - case DP_LANECOUNT_1: - count = (count > 0x1a) ? count : 0x1a; - break; - case DP_LANECOUNT_2: - /* Case for LowResolution and High Audio Sample Rate. */ - offset = dptx_check_res_sample_rate(mtk_dp->edid) ? - 0x04 : 0x00; - count = (count > 0x10) ? count : 0x10 + offset; - break; - case DP_LANECOUNT_4: - default: - count = (count > 0x06) ? count : 0x06; - break; - } - - printk(BIOS_DEBUG, "pixel rate(khz) = %d, sdp_dc_init = %#x\n", - mtk_dp->edid->mode.pixel_clock, count); - - dptx_hal_setsdp_downcnt_init(mtk_dp, count); -} - -static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp) -{ - int pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; - u8 offset; - u16 count = 0; /* count: sdp_down_cnt_init*/ - - switch (mtk_dp->train_info.linklane_count) { - case DP_LANECOUNT_1: - count = 0x20; - break; - case DP_LANECOUNT_2: - offset = dptx_check_res_sample_rate(mtk_dp->edid) ? - 0x14 : 0x00; - count = 0x0018 + offset; - break; - case DP_LANECOUNT_4: - default: - offset = dptx_check_res_sample_rate(mtk_dp->edid) ? - 0x08 : 0x00; - if (pixclk_mhz > mtk_dp->train_info.linkrate * 27) { - count = 0x8; - printk(BIOS_ERR, "Pixclk > LinkRateChange\n"); - } else { - count = 0x10 + offset; - } - break; - } - - dptx_hal_setsdp_downcnt_init_inhblanking(mtk_dp, count); -} - -static void dptx_set_tu(struct mtk_dp *mtk_dp) -{ - u8 bpp; - u16 sram_read_start = DPTX_TBC_BUF_READSTARTADRTHRD; - int tu_size, f_value, pixclk_mhz; - - bpp = dptx_hal_get_colorbpp(mtk_dp); - pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; - tu_size = (640 * pixclk_mhz * bpp) / - (mtk_dp->train_info.linkrate * 27 * - mtk_dp->train_info.linklane_count * 8); - - f_value = tu_size % 10; - printk(BIOS_DEBUG, "TU_size %d, FValue %d\n", tu_size, f_value); - - if (mtk_dp->train_info.linklane_count > 0) { - sram_read_start = mtk_dp->edid->mode.ha / - (mtk_dp->train_info.linklane_count * - 4 * 2 * 2); - sram_read_start = MIN(sram_read_start, - DPTX_TBC_BUF_READSTARTADRTHRD); - dptx_hal_settu_sramrd_start(mtk_dp, sram_read_start); - } - - dptx_hal_settu_setencoder(mtk_dp); - dptx_setsdp_downcnt_init_inhblanking(mtk_dp); - dptx_setsdp_downcnt_init(mtk_dp, sram_read_start); -} - -static void dptx_set_misc(struct mtk_dp *mtk_dp) -{ - u8 format, depth; - union misc_t dptx_misc; - - format = mtk_dp->info.format; - depth = mtk_dp->info.depth; - - /* - * MISC 0/1 reference to spec 1.4a p143 Table 2-96. - * MISC0[7:5] color depth. - */ - dptx_misc.dp_misc.color_depth = depth; - - /* - * MISC0[3]: 0->RGB, 1->YUV - * MISC0[2:1]: 01b->4:2:2, 10b->4:4:4 - */ - switch (format) { - case DP_COLOR_FORMAT_YUV_444: - dptx_misc.dp_misc.color_format = 0x1; - break; - case DP_COLOR_FORMAT_YUV_422: - dptx_misc.dp_misc.color_format = 0x2; - break; - case DP_COLOR_FORMAT_RAW: - dptx_misc.dp_misc.color_format = 0x1; - dptx_misc.dp_misc.spec_def2 = 0x1; - break; - case DP_COLOR_FORMAT_YONLY: - dptx_misc.dp_misc.color_format = 0x0; - dptx_misc.dp_misc.spec_def2 = 0x1; - break; - case DP_COLOR_FORMAT_YUV_420: - case DP_COLOR_FORMAT_RGB_444: - default: - break; - } - - dptx_hal_setmisc(mtk_dp, dptx_misc.cmisc); -} - -static void dptx_set_dptxout(struct mtk_dp *mtk_dp) -{ - dptx_hal_bypassmsa_en(mtk_dp, false); - dptx_set_tu(mtk_dp); -} - static bool dptx_training_checkswingpre(struct mtk_dp *mtk_dp, u8 target_lane_count, const u8 *dpcp202_x, u8 *dpcp_buf) @@ -864,80 +413,6 @@ return DPTX_PASS; } -static void dptx_check_sinkcap(struct mtk_dp *mtk_dp) -{ - u8 buffer[16]; - - memset(buffer, 0x0, sizeof(buffer)); - - buffer[0] = 0x1; - dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, - DPCD_00600, 0x1, buffer); - - mdelay(2); - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - DPCD_00000, 0x10, buffer); - - mtk_dp->train_info.sink_extcap_en = false; - mtk_dp->train_info.dpcd_rev = buffer[0]; - - printk(BIOS_INFO, "SINK DPCD version: %#x\n", - mtk_dp->train_info.dpcd_rev); - - memcpy(mtk_dp->rx_cap, buffer, sizeof(mtk_dp->rx_cap)); - - mtk_dp->rx_cap[14] &= 0x7f; - - if (mtk_dp->train_info.dpcd_rev >= 0x14) - dptx_fec_ready(mtk_dp, FEC_BIT_ERROR_COUNT); - - mtk_dp->train_info.linkrate = MIN(buffer[0x1], - mtk_dp->train_info.sys_max_linkrate); - mtk_dp->train_info.linklane_count = MIN(buffer[2] & 0x1F, - MAX_LANECOUNT); - - mtk_dp->train_info.tps3 = (buffer[2] & BIT(6)) >> 0x6; - mtk_dp->train_info.tps4 = (buffer[3] & BIT(7)) >> 0x7; - - mtk_dp->train_info.down_stream_port_present = (buffer[5] & BIT(0)); - - if ((buffer[3] & BIT(0)) == 0x1) { - printk(BIOS_INFO, "SINK SUPPORT SSC!\n"); - mtk_dp->train_info.sink_ssc_en = true; - } else { - printk(BIOS_INFO, "SINK NOT SUPPORT SSC!\n"); - mtk_dp->train_info.sink_ssc_en = false; - } - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - DPCD_00021, 0x1, buffer); - mtk_dp->train_info.dp_mstcap = (buffer[0] & BIT(0)); - mtk_dp->train_info.dp_mstbranch = false; - - if (mtk_dp->train_info.dp_mstcap == BIT(0)) { - if (mtk_dp->train_info.down_stream_port_present == 0x1) - mtk_dp->train_info.dp_mstbranch = true; - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - DPCD_02003, 0x1, buffer); - if (buffer[0] != 0x0) - dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, - DPCD_02003, 0x1, buffer); - } - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - DPCD_00600, 0x1, buffer); - if (buffer[0] != 0x1) { - buffer[0] = 0x1; - dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, - DPCD_00600, 0x1, buffer); - } - - dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, - DPCD_00200, 0x2, buffer); -} - static void dptx_training_changemode(struct mtk_dp *mtk_dp) { dptx_hal_phyd_reset(mtk_dp); diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c new file mode 100644 index 0000000..8154657 --- /dev/null +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -0,0 +1,398 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/dptx.h> +#include <soc/dptx_hal.h> +#include <soc/dptx_reg.h> +#include <soc/dp_intf.h> +#include <string.h> + +bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *data) +{ + if (retry(7, dptx_hal_auxwrite_bytes(mtk_dp, cmd, dpcd_addr, length, data), + mdelay(1))) + return true; + + printk(BIOS_ERR, "aux write fail: cmd = %d, addr = %#x, len = %ld\n", + cmd, dpcd_addr, length); + + return false; +} + +bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *data) +{ + bool ret = true; + size_t offset = 0; + size_t len; + + while (offset < length) { + len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES); + ret &= dptx_auxwrite_bytes(mtk_dp, cmd, dpcd_addr + offset, + len, data + offset); + offset += len; + } + return ret; +} + +static bool dptx_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, + u32 dpcd_addr, size_t length, u8 *data) +{ + if (retry(7, dptx_hal_auxread_bytes(mtk_dp, cmd, dpcd_addr, length, data), + mdelay(1))) + return true; + + printk(BIOS_ERR, "aux read fail: cmd = %d, addr = %#x, len = %ld\n", + cmd, dpcd_addr, length); + + return false; +} + +bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *rxbuf) +{ + bool ret = true; + size_t offset = 0; + size_t len; + + while (offset < length) { + len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES); + ret &= dptx_auxread_bytes(mtk_dp, cmd, dpcd_addr + offset, + len, rxbuf + offset); + offset += len; + } + return ret; +} + +int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out) +{ + int ret; + u8 edid[ONE_BLOCK_SIZE]; + u8 tmp = 0; + + dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp); + + for (tmp = 0; tmp < ONE_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++) + dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ, + 0x50, DP_AUX_MAX_PAYLOAD_BYTES, + edid + tmp * 16); + + ret = decode_edid(edid, ONE_BLOCK_SIZE, out); + if (ret != EDID_CONFORMANT) { + printk(BIOS_ERR, "failed to decode edid(%d).\n", ret); + return -1; + } + + mtk_dp->edid = out; + return 0; +} + +u8 dptx_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) +{ + return link_status[r - DP_LANE0_1_STATUS]; +} + +u8 dptx_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], int lane) +{ + int i = DP_LANE0_1_STATUS + (lane >> 1); + int s = (lane & 1) * 4; + u8 l = dptx_link_status(link_status, i); + + return (l >> s) & 0xf; +} + +bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) +{ + int lane; + u8 lane_status; + + for (lane = 0; lane < lane_count; lane++) { + lane_status = dptx_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) + return false; + } + return true; +} + +void dptx_videomute(struct mtk_dp *mtk_dp, bool enable) +{ + dptx_hal_videomute(mtk_dp, enable); +} + +static void dptx_fec_ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel) +{ + u8 i, data[3]; + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, 0x90, 0x1, data); + printk(BIOS_DEBUG, "FEC Capable[0], [0:3] should be 1: %#x\n", + data[0]); + + /* + * FEC error count select 120[3:1]: + * 000b: FEC_ERROR_COUNT_DIS + * 001b: UNCORRECTED_BLOCK_ERROR_COUNT + * 010b: CORRECTED_BLOCK_ERROR_COUNT + * 011b: BIT_ERROR_COUNT + * 100b: PARITY_BLOCK_ERROR_COUNT + * 101b: PARITY_BIT_ERROR_COUNT + */ + if (data[0] & BIT(0)) { + mtk_dp->has_fec = true; + data[0] = (err_cnt_sel << 1) | 0x1; + + dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, + 0x120, 0x1, data); + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + 0x280, 0x3, data); + + for (i = 0; i < 3; i++) + printk(BIOS_DEBUG, "FEC status & error Count: %#x\n", + data[i]); + } +} + +void dptx_init_variable(struct mtk_dp *mtk_dp) +{ + mtk_dp->regs = (void *)EDP_BASE; + mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3; + mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2; + mtk_dp->train_info.linklane_count = DP_LANECOUNT_4; + mtk_dp->train_info.sink_extcap_en = false; + mtk_dp->train_info.sink_ssc_en = false; + mtk_dp->train_info.tps3 = true; + mtk_dp->train_info.tps4 = true; + mtk_dp->training_state = DPTX_NTSTATE_STARTUP; + mtk_dp->info.format = DP_COLOR_FORMAT_RGB_444; + mtk_dp->info.depth = DP_COLOR_DEPTH_8BIT; + mtk_dp->power_on = false; + mtk_dp->video_enable = false; + mtk_dp->dp_ready = false; + mtk_dp->has_dsc = false; + mtk_dp->has_fec = false; + mtk_dp->dsc_enable = false; +} + +static inline bool dptx_check_res_sample_rate(const struct edid *edid) +{ + return edid->mode.va + edid->mode.vbl <= 525; +} + +static void dptx_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 sram_read_start) +{ + u32 count = 0; /* count: sdp_down_cnt_init */ + u8 offset; + + if (mtk_dp->edid->mode.pixel_clock > 0) + count = (sram_read_start * 2700 * 8 * + mtk_dp->train_info.linkrate) / + (mtk_dp->edid->mode.pixel_clock * 4); + + switch (mtk_dp->train_info.linklane_count) { + case DP_LANECOUNT_1: + count = (count > 0x1a) ? count : 0x1a; + break; + case DP_LANECOUNT_2: + /* Case for LowResolution and High Audio Sample Rate. */ + offset = dptx_check_res_sample_rate(mtk_dp->edid) ? + 0x04 : 0x00; + count = (count > 0x10) ? count : 0x10 + offset; + break; + case DP_LANECOUNT_4: + default: + count = (count > 0x06) ? count : 0x06; + break; + } + + printk(BIOS_DEBUG, "pixel rate(khz) = %d, sdp_dc_init = %#x\n", + mtk_dp->edid->mode.pixel_clock, count); + + dptx_hal_setsdp_downcnt_init(mtk_dp, count); +} + +static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp) +{ + int pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; + u8 offset; + u16 count = 0; /* count: sdp_down_cnt_init*/ + + switch (mtk_dp->train_info.linklane_count) { + case DP_LANECOUNT_1: + count = 0x20; + break; + case DP_LANECOUNT_2: + offset = dptx_check_res_sample_rate(mtk_dp->edid) ? + 0x14 : 0x00; + count = 0x0018 + offset; + break; + case DP_LANECOUNT_4: + default: + offset = dptx_check_res_sample_rate(mtk_dp->edid) ? + 0x08 : 0x00; + if (pixclk_mhz > mtk_dp->train_info.linkrate * 27) { + count = 0x8; + printk(BIOS_ERR, "Pixclk > LinkRateChange\n"); + } else { + count = 0x10 + offset; + } + break; + } + + dptx_hal_setsdp_downcnt_init_inhblanking(mtk_dp, count); +} + +static void dptx_set_tu(struct mtk_dp *mtk_dp) +{ + u8 bpp; + u16 sram_read_start = DPTX_TBC_BUF_READSTARTADRTHRD; + int tu_size, f_value, pixclk_mhz; + + bpp = dptx_hal_get_colorbpp(mtk_dp); + pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000; + tu_size = (640 * pixclk_mhz * bpp) / + (mtk_dp->train_info.linkrate * 27 * + mtk_dp->train_info.linklane_count * 8); + + f_value = tu_size % 10; + printk(BIOS_DEBUG, "TU_size %d, FValue %d\n", tu_size, f_value); + + if (mtk_dp->train_info.linklane_count > 0) { + sram_read_start = mtk_dp->edid->mode.ha / + (mtk_dp->train_info.linklane_count * + 4 * 2 * 2); + sram_read_start = MIN(sram_read_start, + DPTX_TBC_BUF_READSTARTADRTHRD); + dptx_hal_settu_sramrd_start(mtk_dp, sram_read_start); + } + + dptx_hal_settu_setencoder(mtk_dp); + dptx_setsdp_downcnt_init_inhblanking(mtk_dp); + dptx_setsdp_downcnt_init(mtk_dp, sram_read_start); +} + +void dptx_set_misc(struct mtk_dp *mtk_dp) +{ + u8 format, depth; + union misc_t dptx_misc; + + format = mtk_dp->info.format; + depth = mtk_dp->info.depth; + + /* + * MISC 0/1 reference to spec 1.4a p143 Table 2-96. + * MISC0[7:5] color depth. + */ + dptx_misc.dp_misc.color_depth = depth; + + /* + * MISC0[3]: 0->RGB, 1->YUV + * MISC0[2:1]: 01b->4:2:2, 10b->4:4:4 + */ + switch (format) { + case DP_COLOR_FORMAT_YUV_444: + dptx_misc.dp_misc.color_format = 0x1; + break; + case DP_COLOR_FORMAT_YUV_422: + dptx_misc.dp_misc.color_format = 0x2; + break; + case DP_COLOR_FORMAT_RAW: + dptx_misc.dp_misc.color_format = 0x1; + dptx_misc.dp_misc.spec_def2 = 0x1; + break; + case DP_COLOR_FORMAT_YONLY: + dptx_misc.dp_misc.color_format = 0x0; + dptx_misc.dp_misc.spec_def2 = 0x1; + break; + case DP_COLOR_FORMAT_YUV_420: + case DP_COLOR_FORMAT_RGB_444: + default: + break; + } + + dptx_hal_setmisc(mtk_dp, dptx_misc.cmisc); +} + +void dptx_set_dptxout(struct mtk_dp *mtk_dp) +{ + dptx_hal_bypassmsa_en(mtk_dp, false); + dptx_set_tu(mtk_dp); +} + +void dptx_check_sinkcap(struct mtk_dp *mtk_dp) +{ + u8 buffer[16]; + + memset(buffer, 0x0, sizeof(buffer)); + + buffer[0] = 0x1; + dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, + DPCD_00600, 0x1, buffer); + + mdelay(2); + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + DPCD_00000, 0x10, buffer); + + mtk_dp->train_info.sink_extcap_en = false; + mtk_dp->train_info.dpcd_rev = buffer[0]; + + printk(BIOS_INFO, "SINK DPCD version: %#x\n", + mtk_dp->train_info.dpcd_rev); + + memcpy(mtk_dp->rx_cap, buffer, sizeof(mtk_dp->rx_cap)); + + mtk_dp->rx_cap[14] &= 0x7f; + + if (mtk_dp->train_info.dpcd_rev >= 0x14) + dptx_fec_ready(mtk_dp, FEC_BIT_ERROR_COUNT); + + mtk_dp->train_info.linkrate = MIN(buffer[0x1], + mtk_dp->train_info.sys_max_linkrate); + mtk_dp->train_info.linklane_count = MIN(buffer[2] & 0x1F, + MAX_LANECOUNT); + + mtk_dp->train_info.tps3 = (buffer[2] & BIT(6)) >> 0x6; + mtk_dp->train_info.tps4 = (buffer[3] & BIT(7)) >> 0x7; + + mtk_dp->train_info.down_stream_port_present = (buffer[5] & BIT(0)); + + if ((buffer[3] & BIT(0)) == 0x1) { + printk(BIOS_INFO, "SINK SUPPORT SSC!\n"); + mtk_dp->train_info.sink_ssc_en = true; + } else { + printk(BIOS_INFO, "SINK NOT SUPPORT SSC!\n"); + mtk_dp->train_info.sink_ssc_en = false; + } + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + DPCD_00021, 0x1, buffer); + mtk_dp->train_info.dp_mstcap = (buffer[0] & BIT(0)); + mtk_dp->train_info.dp_mstbranch = false; + + if (mtk_dp->train_info.dp_mstcap == BIT(0)) { + if (mtk_dp->train_info.down_stream_port_present == 0x1) + mtk_dp->train_info.dp_mstbranch = true; + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + DPCD_02003, 0x1, buffer); + if (buffer[0] != 0x0) + dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, + DPCD_02003, 0x1, buffer); + } + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + DPCD_00600, 0x1, buffer); + if (buffer[0] != 0x1) { + buffer[0] = 0x1; + dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, + DPCD_00600, 0x1, buffer); + } + + dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, + DPCD_00200, 0x2, buffer); +} diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index 99b2ac2..63c9dbb 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -7,6 +7,144 @@ #define ENABLE_DPTX_EF_MODE 0x1 #define DPTX_AUX_SET_ENAHNCED_FRAME 0x80 +#define ONE_BLOCK_SIZE 128 + +#define DP_LINK_CONSTANT_N_VALUE 0x8000 +#define DP_LINK_STATUS_SIZE 6 + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +#define DP_LANE_CR_DONE (1 << 0) +#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +#define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_BRANCH_OUI_HEADER_SIZE 0xc +#define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 +#define DP_LTTPR_COMMON_CAP_SIZE 8 +#define DP_LTTPR_PHY_CAP_SIZE 3 + +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e +#define DP_TRAINING_AUX_RD_MASK 0x7f +#define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) + +#define DP_EDP_DPCD_REV 0x700 +#define DP_EDP_11 0x00 +#define DP_EDP_12 0x01 +#define DP_EDP_13 0x02 +#define DP_EDP_14 0x03 +#define DP_EDP_14a 0x04 +#define DP_EDP_14b 0x05 + +/* Receiver Capability */ +#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV_10 0x10 +#define DP_DPCD_REV_11 0x11 +#define DP_DPCD_REV_12 0x12 +#define DP_DPCD_REV_13 0x13 +#define DP_DPCD_REV_14 0x14 + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 +#define DP_RECEIVE_PORT_0_STATUS (1 << 0) +#define DP_RECEIVE_PORT_1_STATUS (1 << 1) +#define DP_STREAM_REGENERATION_STATUS (1 << 2) + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + +#define MAX_LANECOUNT 4 + +enum { + DP_LANECOUNT_1 = 0x1, + DP_LANECOUNT_2 = 0x2, + DP_LANECOUNT_4 = 0x4, +}; + +enum { + DP_VERSION_11 = 0x11, + DP_VERSION_12 = 0x12, + DP_VERSION_14 = 0x14, + DP_VERSION_12_14 = 0x16, + DP_VERSION_14_14 = 0x17, + DP_VERSION_MAX, +}; + +enum { + DPTX_SWING0 = 0x00, + DPTX_SWING1 = 0x01, + DPTX_SWING2 = 0x02, + DPTX_SWING3 = 0x03, +}; + +enum { + DPTX_PREEMPHASIS0 = 0x00, + DPTX_PREEMPHASIS1 = 0x01, + DPTX_PREEMPHASIS2 = 0x02, + DPTX_PREEMPHASIS3 = 0x03, +}; + +enum { + DPTX_PASS = 0, + DPTX_PLUG_OUT = 1, + DPTX_TIMEOUT = 2, + DPTX_AUTH_FAIL = 3, + DPTX_EDID_FAIL = 4, + DPTX_TRANING_FAIL = 5, + DPTX_TRANING_STATE_CHANGE = 6, +}; + +enum { + FEC_ERROR_COUNT_DISABLE = 0x0, + FEC_UNCORRECTED_BLOCK_ERROR_COUNT = 0x1, + FEC_CORRECTED_BLOCK_ERROR_COUNT = 0x2, + FEC_BIT_ERROR_COUNT = 0x3, + FEC_PARITY_BLOCK_ERROR_COUNT = 0x4, + FEC_PARITY_BIT_ERROR_COUNT = 0x5, +}; + +enum { + DPTX_NTSTATE_STARTUP = 0x0, + DPTX_NTSTATE_CHECKCAP = 0x1, + DPTX_NTSTATE_CHECKEDID = 0x2, + DPTX_NTSTATE_TRAINING_PRE = 0x3, + DPTX_NTSTATE_TRAINING = 0x4, + DPTX_NTSTATE_CHECKTIMING = 0x5, + DPTX_NTSTATE_NORMAL = 0x6, + DPTX_NTSTATE_POWERSAVE = 0x7, + DPTX_NTSTATE_DPIDLE = 0x8, + DPTX_NTSTATE_MAX, +}; + +enum { + DPTX_DISP_NONE = 0, + DPTX_DISP_RESUME = 1, + DPTX_DISP_SUSPEND = 2, +}; + +enum { + TRAIN_STEP_SUCCESS = 0, + TRAIN_STEP_FAIL_BREAK = 1, + TRAIN_STEP_FAIL_NOT_BREAK = 2, +}; + +#define DPTX_TRAIN_RETRY_LIMIT 0x8 +#define DPTX_TRAIN_MAX_ITERATION 0x5 + +#define HPD_INT_EVNET BIT(3) +#define HPD_CONNECT BIT(2) +#define HPD_DISCONNECT BIT(1) +#define HPD_INITIAL_STATE 0 + union misc_t { struct { u8 is_sync_clock : 1; @@ -73,5 +211,21 @@ }; int mtk_edp_init(struct edid *edid); +u8 dptx_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); +bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count); +bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *data); +bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *data); +void dptx_videomute(struct mtk_dp *mtk_dp, bool enable); +void dptx_set_dptxout(struct mtk_dp *mtk_dp); +void dptx_set_misc(struct mtk_dp *mtk_dp); +void dptx_init_variable(struct mtk_dp *mtk_dp); +void dptx_check_sinkcap(struct mtk_dp *mtk_dp); +int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out); +bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, + size_t length, u8 *rxbuf); +u8 dptx_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r); #endif /* SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H */ diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index 3c5965b..c09317e 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -39,6 +39,7 @@ ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/display.c +ramstage-y += ../common/dp/dptx_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index f011f95..85e261e 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -50,6 +50,7 @@ ramstage-y += ../common/display.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c +ramstage-y += ../common/dp/dptx_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += emi.c ramstage-y += hdmi.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85859?usp=email ) Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 12 files changed, 60 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/1 diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h similarity index 97% rename from src/soc/mediatek/common/dp/include/soc/dp_intf.h rename to src/soc/mediatek/common/dp/include/soc/dp_intf_common.h index 240a7e2..fceeb6d 100644 --- a/src/soc/mediatek/common/dp/include/soc/dp_intf.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_H -#define SOC_MEDIATEK_COMMON_DP_DP_INTF_H +#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H #include <edid.h> #include <types.h> @@ -264,4 +264,4 @@ void dp_intf_config(const struct edid *edid); -#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h similarity index 89% rename from src/soc/mediatek/common/dp/include/soc/dptx.h rename to src/soc/mediatek/common/dp/include/soc/dptx_common.h index b473301..99b2ac2 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H #define DPTX_TBC_BUF_READSTARTADRTHRD 0x08 #define ENABLE_DPTX_EF_MODE 0x1 @@ -74,4 +74,4 @@ int mtk_edp_init(struct edid *edid); -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h similarity index 95% rename from src/soc/mediatek/common/dp/include/soc/dptx_hal.h rename to src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index d430b6a..778fe46 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H #define AUX_CMD_I2C_R_MOT0 0x1 #define AUX_CMD_I2C_R 0x5 @@ -100,4 +100,4 @@ void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value); void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable); -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h similarity index 99% rename from src/soc/mediatek/common/dp/include/soc/dptx_reg.h rename to src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h index a385eb8..a79c31f 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_reg.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H #define TOP_OFFSET 0x2000 #define ENC0_OFFSET 0x3000 @@ -4737,4 +4737,4 @@ #define DPCD_69494 0x69494 #define DPCD_69518 0x69518 -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/dp_intf.h b/src/soc/mediatek/mt8188/include/soc/dp_intf.h new file mode 100644 index 0000000..404174e --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dp_intf.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ + +#include <soc/dp_intf_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx.h b/src/soc/mediatek/mt8188/include/soc/dptx.h new file mode 100644 index 0000000..8ba95b0 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ + +#include <soc/dptx_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h new file mode 100644 index 0000000..4cf1e62 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ + +#include <soc/dptx_hal_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_reg.h b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h new file mode 100644 index 0000000..6b768f6 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ + +#include <soc/dptx_reg_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dp_intf.h b/src/soc/mediatek/mt8195/include/soc/dp_intf.h new file mode 100644 index 0000000..822b5fa --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dp_intf.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ + +#include <soc/dp_intf_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/mt8195/include/soc/dptx.h new file mode 100644 index 0000000..60eb917 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ + +#include <soc/dptx_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h new file mode 100644 index 0000000..1409310 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ + +#include <soc/dptx_hal_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h new file mode 100644 index 0000000..edf9a1a --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h @@ -0,0 +1,6 @@ +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ + +#include <soc/dptx_reg_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

1 0

[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Alok Agarwal, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, Vikrant L Jadeja. srinivas.kulkarni(a)intel.com has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85750?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85750?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788a0d2373593bc7bd447dd37150ec4fda6d6bb4 Gerrit-Change-Number: 85750 Gerrit-PatchSet: 4 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 05:34:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 3: Code-Review+1 (4 comments) File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/aea22df5_c0b7235f?us… : PS3, Line 49: * when 1GB PT aren't supported it maps 40 bits of the address space (512GiB). IMO the x86_64 by default boot with 4-level paging and here the 40bit VA is mainly for consideration of page table size, right? https://review.coreboot.org/c/coreboot/+/85806/comment/c804c538_b211ecf2?us… : PS3, Line 61: Not sure if macros could be used to represent the constants, e.g. 512ULL, as (1 << PDPT_BITS)? https://review.coreboot.org/c/coreboot/+/85806/comment/e03e2b85_2c85803f?us… : PS3, Line 157: */ It would be helpful if we could have comments here as well, e.g. When 1GB PT are supported it maps 48 bits (the maximum 4-LVL paging supports), when 1GB PT aren't supported it maps 40 bits of the address space (512GiB). https://review.coreboot.org/c/coreboot/+/85806/comment/c29e7fe1_89a0d1b6?us… : PS3, Line 160: /* Using 512 4K pages limits the usable address space */ Do we need to make sure the CPU is not working under 5-level paging? (though coreboot never enables it). -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 05:34:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

← Newer
1
...
52
53
54
55
56
57
58
...
83
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025