coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix
by Sean Rhodes (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86133?usp=email ) Change subject: soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86133/comment/7b8c6b61_0f353e1f?us… : PS3, Line 7: meteorlake > `mtl,ptl,tgl` might help to fit the title line < 72 ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Gerrit-Change-Number: 86133 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 08:34:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix
by Sean Rhodes (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86133?usp=email to look at the new patch set (#4). Change subject: soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix ...................................................................... soc/intel/{mtl,ptl,tgl}: Fix incorrect reporting of S0ix If S0ix is not enabled, then it should not be reported that it is supported. TEST=boot linux on starlabs boards, check s2idle isn't listed under `/sys/power/mem_sleep`. Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/meteorlake/cpu.c M src/soc/intel/pantherlake/cpu.c M src/soc/intel/tigerlake/lpm.c 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86133/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Gerrit-Change-Number: 86133 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Add check to pmc_/gpe0_different_values
by Sean Rhodes (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun, Werner Zeh. Sean Rhodes has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Add check to pmc_/gpe0_different_values ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 08:33:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Revert "mb/google/fatcat: Enable SAGv"
by Subrata Banik (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86154?usp=email ) Change subject: Revert "mb/google/fatcat: Enable SAGv" ...................................................................... Patch Set 2: Code-Review-2 (1 comment) Patchset: PS2: Looks like only one board has reported this issue so far, will keep eye on it -- To view, visit https://review.coreboot.org/c/coreboot/+/86154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b Gerrit-Change-Number: 86154 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 07:24:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel: Add check to pmc_/gpe0_different_values
by Subrata Banik (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86164?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Add check to pmc_/gpe0_different_values ...................................................................... soc/intel: Add check to pmc_/gpe0_different_values The pmc_/gpe0_different_values function previously only checked if the dw0, dw1, and dw2 values were different from each other. This commit adds a check to ensure that the values are not all zero, as this can represent an invalid configuration. This prevents potential issues arising from a zeroed configuration by ensuring the assertion only passes if the values are different and at least one of them is non-zero. TEST=Built and booted normally. No assertion failure observed. Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 9 files changed, 63 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86164/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique
by Subrata Banik (Code Review) 27 Jan '25

27 Jan '25

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85161?usp=email ) Change subject: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > > Yes, this is an option for sure but this is still a W/A because 0 means some GPIO community as well that you are programming as Tire-1 GPE. So, each DWORD register sets the 0 values means all GPE will be masked. > > > > if dw0/dw1/dw2 are all zero when passed to `pmc_gpe_init()`, then the POR values are used, so zeros are not programmed. 0/0/0 isn't a valid GPE routing config anyway, so we can use that to fall back on the POR values, and still check if someone has misconfigured via the assert - just carve out one exception > > > As per EDS, 0 for any DW is a valid value but let me get back with some code change and share with you. https://review.coreboot.org/c/coreboot/+/86164 please review -- To view, visit https://review.coreboot.org/c/coreboot/+/85161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Gerrit-Change-Number: 85161 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 06:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel: Add check to pmc_/gpe0_different_values
by Subrata Banik (Code Review) 27 Jan '25

27 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Add check to pmc_/gpe0_different_values ...................................................................... soc/intel: Add check to pmc_/gpe0_different_values The pmc_/gpe0_different_values function previously only checked if the dw0, dw1, and dw2 values were different from each other. This commit adds a check to ensure that the values are not all zero, as this can represent an invalid configuration. This prevents potential issues arising from a zeroed configuration by ensuring the assertion only passes if the values are different and at least one of them is non-zero. TEST=Built and booted normally. No assertion failure observed. Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 9 files changed, 68 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86164/1 diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 60d6e10..3dc25af 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -156,9 +156,15 @@ static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 5366ca8..9ed39f5 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -140,9 +140,15 @@ static void gpe0_different_values(const struct soc_intel_apollolake_config *config) { + bool all_zero = (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0) && + (config->gpe0_dw3 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->gpe0_dw1 != config->gpe0_dw2) && (config->gpe0_dw1 != config->gpe0_dw3) && - (config->gpe0_dw2 != config->gpe0_dw3); + (config->gpe0_dw2 != config->gpe0_dw3) && + !all_zero; assert(result); } diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 63eed16..43595a3 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -150,9 +150,15 @@ static void gpe0_different_values(const struct soc_intel_cannonlake_config *config) { + bool all_zero = (config->gpe0_dw0 == 0) && + (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->gpe0_dw0 != config->gpe0_dw1) && (config->gpe0_dw0 != config->gpe0_dw2) && - (config->gpe0_dw1 != config->gpe0_dw2); + (config->gpe0_dw1 != config->gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index a862bdd..ec0a249 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -147,11 +147,17 @@ return (uint32_t *)(soc_read_pmc_base() + ETR); } -static void pmc_gpe0_different_values(const struct soc_intel_elkhartlake_config *config) +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 569eac7..fb8b173 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -147,11 +147,17 @@ return (uint32_t *)(soc_read_pmc_base() + ETR); } -static void pmc_gpe0_different_values(const struct soc_intel_jasperlake_config *config) +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 154c3be..93a84dc 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -150,11 +150,17 @@ return (uint32_t *)(soc_read_pmc_base() + ETR); } -static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config) +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 306d834..2fce050 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -145,11 +145,17 @@ return (uint32_t *)(soc_read_pmc_base() + ETR); } -static void pmc_gpe0_different_values(const struct soc_intel_pantherlake_config *config) +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index ed1ab8b..212cbe5 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -156,9 +156,15 @@ static void gpe0_different_values(const struct soc_intel_skylake_config *config) { + bool all_zero = (config->gpe0_dw0 == 0) && + (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->gpe0_dw0 != config->gpe0_dw1) && (config->gpe0_dw0 != config->gpe0_dw2) && - (config->gpe0_dw1 != config->gpe0_dw2); + (config->gpe0_dw1 != config->gpe0_dw2) && + !all_zero; assert(result); } diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 7903264..151870b 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -153,11 +153,17 @@ return (uint32_t *)(soc_read_pmc_base() + ETR); } -static void pmc_gpe0_different_values(const struct soc_intel_tigerlake_config *config) +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && - (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2) && + !all_zero; assert(result); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Apply GPIO configuration lock
by Cliff Huang (Code Review) 27 Jan '25

27 Jan '25

Cliff Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84902?usp=email ) Change subject: mb/google/fatcat: Apply GPIO configuration lock ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc991910b9d3f2dae4b1a07bcf16ad7ac4bc61ca Gerrit-Change-Number: 84902 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration
by Cliff Huang (Code Review) 27 Jan '25

27 Jan '25

Cliff Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email ) Change subject: soc/intel/common/gpio: add function to lock GPIO configuration ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabe4e4b1d282a5f6cae8f330100c9139e0c2691d Gerrit-Change-Number: 84901 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>

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[M] Change in coreboot[main]: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique
by Subrata Banik (Code Review) 27 Jan '25

27 Jan '25

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85161?usp=email ) Change subject: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > Yes, this is an option for sure but this is still a W/A because 0 means some GPIO community as well that you are programming as Tire-1 GPE. So, each DWORD register sets the 0 values means all GPE will be masked. > > if dw0/dw1/dw2 are all zero when passed to `pmc_gpe_init()`, then the POR values are used, so zeros are not programmed. 0/0/0 isn't a valid GPE routing config anyway, so we can use that to fall back on the POR values, and still check if someone has misconfigured via the assert - just carve out one exception As per EDS, 0 for any DW is a valid value but let me get back with some code change and share with you. -- To view, visit https://review.coreboot.org/c/coreboot/+/85161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Gerrit-Change-Number: 85161 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 04:22:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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