coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
by Karthik Ramasubramanian (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86111/comment/91965b7e_47c7adab?us… : PS4, Line 202: ps->prev_sleep_state == ACPI_S5 > We are only issuing a warm reset post UFS disablement in the S5 flow. […] When the isssue happens, the previous sleep state is read as S0. We have always asssociated this with warm reset. But CSE FW status register does not indicate warm reset. CSE FW status register reads as `ME: HFSTS2 : 0x3B850106`. Bits 24 - 27 (0xB) indicate the reset type as `Power cycle reset through CMoff`. If it were warm reset, bits 24 - 27 would read as 0x9. So in addition to S5 reset, if we also trigger a warm reset for any other non warm reset as indicated in CSE FW status register, that will simplify the solution for this issue a lot. -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Jan 2025 16:47:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: cpu/x86/mp_init: Add code to restart APs
by Filip Lewiński (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Jérémy Compostella, Krystian Hebel, Michał Kopeć, Michał Żygowski, Michał Żygowski, Paul Menzel. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82696?usp=email ) Change subject: cpu/x86/mp_init: Add code to restart APs ...................................................................... Patch Set 9: (1 comment) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/82696/comment/4871c2c9_e11a10d7?us… : PS7, Line 1215: printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", > It is just the same as in mp_init function. @coreboot.org@gmail.com Can we mark this as resolved? -- To view, visit https://review.coreboot.org/c/coreboot/+/82696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief2a7629d3075de29b363d05330e3a76cef48971 Gerrit-Change-Number: 82696 Gerrit-PatchSet: 9 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 16:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: coreboot org <coreboot.org(a)gmail.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Christian Walter, Julius Werner, Michał Żygowski. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82695?usp=email ) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... Patch Set 12: (3 comments) File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/82695/comment/df5b050b_a64871ac?us… : PS5, Line 62: if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK) && !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { > Sorry, I'm still not really following to be honest. […] @jwerner@chromium.org Thank you for your detailed feedback and patience in this discussion. To address your concerns: * I've added `&& !VBOOT_STARTS_IN_BOOTBLOCK` and `select TPM_STARTUP_IGNORE_POSTINIT` to the [Intel TXT Kconfig option](https://review.coreboot.org/c/coreboot/+/82695/12/src/security/inte… * I've removed the `!STARTS_IN_BOOTBLOCK` from [bootblock.c](https://review.coreboot.org/c/coreboot/+/82695/12/src/lib/boot… File src/security/tpm/Kconfig: https://review.coreboot.org/c/coreboot/+/82695/comment/99e2e257_06247098?us… : PS9, Line 125: depends on TPM_MEASURED_BOOT > This is still going to clash with the "vboot in PSP" thing the AMD CPUs are doing, so since you prob […] [Done](https://review.coreboot.org/c/coreboot/+/82695/12/src/security/tpm/Kc… File src/security/vboot/tpm_common.c: https://review.coreboot.org/c/coreboot/+/82695/comment/0d3d0b66_0cda20ce?us… : PS9, Line 24: && !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) > I don't really understand the second part here? Even in the VBOOT_STARTS_IN_BOOTBLOCK case, the MEAS […] [Removed](https://review.coreboot.org/c/coreboot/+/82695/12/src/security/vbo… the redundant condition -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 12 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Jan 2025 16:29:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Filip Lewiński <filip.lewinski(a)3mdeb.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Christian Walter, Filip Lewiński. Hello Christian Walter, Michał Żygowski, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82695?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... security: Allow vboot when INTEL_TXT enabled INTEL_TXT mandates usage of TPM_MEASURED_BOOT_INIT_BOOTBLOCK, which is not compatible with VBOOT. This essentially making VBOOT and INTEL_TXT mutually exclusive, but they do not have to be. Do not call tpm_setup in bootblock_main if vboot starts in bootblock, it would only start the TPM slightly faster. Most platforms probably start vboot in bootblock, so there will be no loss of tpm_setup state. If vboot does not start in bootblock and TPM_MEASURED_BOOT_INIT_BOOTBLOCK is enabled, skip the tpm_setup and simply initialize the TLCL library. TEST=Run VP4670 with INTEL_TXT and VBOOT enabled. Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/lib/bootblock.c M src/security/intel/txt/Kconfig M src/security/tpm/Kconfig M src/security/vboot/tpm_common.c 4 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82695/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 12 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Christian Walter, Filip Lewiński. Hello Christian Walter, Michał Żygowski, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82695?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... security: Allow vboot when INTEL_TXT enabled INTEL_TXT mandates usage of TPM_MEASURED_BOOT_INIT_BOOTBLOCK, which is not compatible with VBOOT. This essentially making VBOOT and INTEL_TXT mutually exclusive, but they do not have to be. Do not call tpm_setup in bootblock_main if vboot starts in bootblock, it would only start the TPM slightly faster. Most platforms probably start vboot in bootblock, so there will be no loss of tpm_setup state. If vboot does not start in bootblock and TPM_MEASURED_BOOT_INIT_BOOTBLOCK is enabled, skip the tpm_setup and simply initialize the TLCL library. TEST=Run VP4670 with INTEL_TXT and VBOOT enabled. Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/lib/bootblock.c M src/security/intel/txt/Kconfig M src/security/tpm/Kconfig M src/security/vboot/tpm_common.c 4 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82695/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 10 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel: Add check to pmc_/gpe0_different_values
by Matt DeVillier (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun, Werner Zeh. Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Add check to pmc_/gpe0_different_values ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Or we can add a debug message stating that GPEs are disabled. right, zero is a valid GPE route. But is all 3 being zero? Right now, that's being used to indicate that the mainboard has not programmed any GPE routes and that the default POR values should be used. -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 13:46:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook: Only show Hyper-Threading option when relevant
by Matt DeVillier (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86166?usp=email ) Change subject: mb/starlabs/starbook: Only show Hyper-Threading option when relevant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929 Gerrit-Change-Number: 86166 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 27 Jan 2025 13:43:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/pcie_gpp.c: Add PCI routing table
by Felix Held (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/85019?usp=email ) Change subject: soc/amd/glinda/pcie_gpp.c: Add PCI routing table ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: either the fsp should provide a valid irq routing table hob or we should read the config that the fsp has applied from the registers; probalen with that is that the indices of the two sets of registers don't necessarily have a 1:1 mapping. i think that having this config basically hard-coded in both fsp and coreboot has the potential for things to break when one side is changed, but the other isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/85019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c11205ecc1554451a5e9d8f05102fd0d4d25ad Gerrit-Change-Number: 85019 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 13:40:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Kapil Porwal (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Jamie Ryu, Pranava Y N. Kapil Porwal has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) Change subject: mb/google/fatcat: Enable s0ix ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 12:04:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/{adl_n,mtl}: Don't configure GPE routes
by Eric Lai (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Eric Lai has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86165?usp=email ) Change subject: mb/starlabs/starbook/{adl_n,mtl}: Don't configure GPE routes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0 Gerrit-Change-Number: 86165 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 12:03:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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