coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86169/comment/ee029777_88981a38?us… : PS1, Line 9: Introduce an API to read the CSME host firmware status register for > nit: Introduce an API to read the CSME (Converged Security and Management Engine) host firmware stat […] Done File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/42fcdc8d_869accf1?us… : PS1, Line 302: #define ME_HFSTS2_CUR_PM_EVENT_MASK (0xF << ME_HFSTS2_CUR_PM_EVENT_SHIFT) > Usually coreboot uses lower case for hexadecimal constant values. Done https://review.coreboot.org/c/coreboot/+/86169/comment/aee4970a_13cf68e8?us… : PS1, Line 303: static uint8_t cse_get_hfs2_current_pm_event(void) > nit: An empty line would be nice. Done File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/86169/comment/3a8e692c_4d16b496?us… : PS1, Line 387: PWR_CYCLE_RESET_CMOFF = 0xB, > Usually coreboot uses lower case for hexadecimal constant values. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 23:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86169/comment/99db2725_7139ff15?us… : PS1, Line 9: Introduce an API to read the CSME host firmware status register for > nit: Introduce an API to read the CSME (Converged Security and Management Engine) host firmware stat […] Done File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/4ee1c519_e0746040?us… : PS1, Line 302: #define ME_HFSTS2_CUR_PM_EVENT_MASK (0xF << ME_HFSTS2_CUR_PM_EVENT_SHIFT) > Usually coreboot uses lower case for hexadecimal constant values. Done https://review.coreboot.org/c/coreboot/+/86169/comment/5c0b6199_ac6fc678?us… : PS1, Line 303: static uint8_t cse_get_hfs2_current_pm_event(void) > nit: An empty line would be nice. Done File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/86169/comment/c17a8f91_88356f05?us… : PS1, Line 387: PWR_CYCLE_RESET_CMOFF = 0xB, > Usually coreboot uses lower case for hexadecimal constant values. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 23:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Hello Intel coreboot Reviewers, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86169?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... soc/intel/common/block/cse: Add API to match current PM event Introduce an API to read the Converged Security and Management Engine (CSME) host firmware status register to obtain the current Power Management event and compare it with a specified input event. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86169/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Jérémy Compostella (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86169/comment/ee1980b0_d7efd8ce?us… : PS1, Line 9: Introduce an API to read the CSME host firmware status register for nit: Introduce an API to read the CSME (Converged Security and Management Engine) host firmware status register to obtain the current Power Management event and compare it with a specified input event. File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/7a616d50_0dd6baff?us… : PS1, Line 302: #define ME_HFSTS2_CUR_PM_EVENT_MASK (0xF << ME_HFSTS2_CUR_PM_EVENT_SHIFT) Usually coreboot uses lower case for hexadecimal constant values. https://review.coreboot.org/c/coreboot/+/86169/comment/3736bf94_1a9eeb42?us… : PS1, Line 303: static uint8_t cse_get_hfs2_current_pm_event(void) nit: An empty line would be nice. File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/86169/comment/35416898_ace2048d?us… : PS1, Line 387: PWR_CYCLE_RESET_CMOFF = 0xB, Usually coreboot uses lower case for hexadecimal constant values. -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 22:56:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Jamie Ryu (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Paul Menzel, Pranava Y N. Jamie Ryu has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) Change subject: mb/google/fatcat: Enable s0ix ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84923/comment/12f74635_0a61dc0b?us… : PS1, Line 8: > Please elaborate. Why was it disabled, and why is it safe to enable now? […] We disable s0ix at the beginning of the program and enable once s0ix is verified and stable. s0ix is internally verified and working; hence, I tried to enable it on the baseline, but we noticed this week s0ix is failing with ToT. The debug is in progress and I will update the commit msg and resolve the comments once the issue is root caused. -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 22:55:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Karthik Ramasubramanian (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86170/comment/fa51b9fd_ab223305?us… : PS1, Line 203: cse_match_current_pm_event(PWR_CYCLE_RESET_CMOFF)) && > Unexpected tab character in before `&&` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Jan 2025 22:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Hello Intel coreboot Reviewers, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86169?usp=email to look at the new patch set (#2). Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... soc/intel/common/block/cse: Add API to match current PM event Introduce an API to read the CSME host firmware status register for current Power Management event and match it against an input event. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86169/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Karthik Ramasubramanian (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86170?usp=email to look at the new patch set (#2). Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... soc/intel/alderlake/romstage: Update UFS disable sequence Currently after UFS is disabled, if the device is coming out of S5 sleep state then a warm reset is triggered such that PMC samples the UFS function disable bit and disables the UFS controller accordingly. Sometimes during the boot flow, an additional kind of reset gets triggered - Power cycle Reset through CMoff. Hence initiate a warm reset when the host comes out of S5 sleep state or Power cycle Reset through CMoff. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode an extra warm reset is triggered such that the UFS controller is disabled. Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86170/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/erying/tgl: Drop specifying which timers to use
by Alicja Michalska (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Angel Pons, Matt DeVillier. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86093?usp=email ) Change subject: mb/erying/tgl: Drop specifying which timers to use ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86093/comment/a6b65c5d_4dddd2f3?us… : PS2, Line 1: Parent: 9dee482a (mb/google/nissa/var/telith: Configure Acoustic noise mitigation) > I'm confused, the Kconfigs in question aren't about X2APIC Right, sorry, two separate things. This one is about recovering from "sleep". Mainboard has broken S3 state, so I left s0ix enabled (after removing `HAVE_ACPI_RESUME`. However, if legacy timer is enabled, system will hang when it's trying to enter s0ix. Without any of those timers enabled, system "enters" s0ix state and stays there until you press a button on the keyboard/case to wake it up. It only enters it partially since SIO doesn't cut the power, but at least you can recover from accidental sleep state without losing your data. -- To view, visit https://review.coreboot.org/c/coreboot/+/86093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e0ac1d289447c292a49111251d321c951078e2 Gerrit-Change-Number: 86093 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 22:39:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Jérémy Compostella (Code Review) 27 Jan '25

27 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86170/comment/92a323d1_8bffffb4?us… : PS1, Line 203: cse_match_current_pm_event(PWR_CYCLE_RESET_CMOFF)) && Unexpected tab character in before `&&` -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 22:29:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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