coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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3270 discussions

[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Sowmya Aralguppe (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 01:29:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: fatcat-ish: disable UART0 RX
by Li1 Feng (Code Review) 28 Jan '25

28 Jan '25

Li1 Feng has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email ) Change subject: fatcat-ish: disable UART0 RX ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 00:39:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... util/crossgcc/buildgcc: Add riscv64-elf to targets All of the other targets support invoking the build with the full target arch name. RISC does not. Update the script to allow riscv64-elf to invoke the build the same way that riscv-elf does to minimize name mangling and exceptions for the architecture name in paths. Leave riscv-elf in tact as an option so we don't break anyone else. BUG=None TEST=./util/crossgcc/buildgcc --platform riscv64-elf Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86171/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4963462..8484ed0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1010,7 +1010,8 @@ x86_64*) TARGETARCH=x86_64-elf;; i386-elf) ;; i386-mingw32) ;; - riscv-elf) TARGETARCH=riscv64-elf + riscv-elf | riscv64-elf) + TARGETARCH=riscv64-elf TARGET_GCC_OPTIONS="$TARGET_GCC_OPTIONS --with-isa-spec=20191213" TARGET_BINUTILS_OPTIONS="$TARGET_BINUTILS_OPTIONS --with-isa-spec=20191213";; powerpc64*-linux*) ;; -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add pi_img loader in ramstage
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86161?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add pi_img loader in ramstage ...................................................................... soc/mediatek/mt8196: Add pi_img loader in ramstage This patch includes loading pi_img through CBFS and passing parameters of pi_img to mtk_fsp for parsing. BUG=b:373797027 TEST=Build pass. boot ok. Locd pi_img with following logs: CBFS: Found 'pi_img.img' @0xb2340 size 0x9620 in mcache @0xfffdd440 read SPI 0x4b43a0 0x9620: 2946 us, 13045 KB/s, 104.360 Mbps VB2:vb2_digest_init() 38432 bytes, hash algo 2, HW acceleration enabled mtk_init_mcu: Loaded (and reset) pi_img.img in 3 msecs (180421 bytes) Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86161 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/mtk_fsp_common.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/pi_image.h A src/soc/mediatek/mt8196/pi_image.c M src/soc/mediatek/mt8196/soc.c 6 files changed, 69 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h index 29e7ed9..bc0d92c 100644 --- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -16,6 +16,7 @@ FSP_STATUS_PARAM_NOT_FOUND, FSP_STATUS_PARAM_INVALID_SIZE, FSP_STATUS_INVALID_STORAGE, + FSP_STATUS_INVALID_PI_IMG, }; enum fsp_phase { @@ -38,6 +39,8 @@ /* 0x40000000+ reserved for input type params */ FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), FSP_PARAM_TYPE_STORAGE, + FSP_PARAM_TYPE_PI_IMG, + FSP_PARAM_TYPE_PI_IMG_CSRAM, /* 0x80000000+ reserved for output type params */ FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index fe89288..9d27a5f 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -39,6 +39,13 @@ help The file name of the MediaTek DPM PM firmware. +config PI_IMG_FIRMWARE + string + default "pi_img.img" + help + The file name of the MediaTek PI_IMG firmware. The main purpose of the pi_img is to + pass various frequency and voltage scaling parameters and settings to MCUPM. + config SSPM_FIRMWARE string default "sspm.bin" diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 4cf1660..d780ebd 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -75,6 +75,7 @@ ramstage-y += mt6685_rtc.c ramstage-y += mtcmos.c ramstage-y += ../common/mtk_fsp.c +ramstage-y += pi_image.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c sspm_sram.c @@ -97,6 +98,7 @@ $(CONFIG_DPM_PM_FIRMWARE) \ $(CONFIG_GPUEB_FIRMWARE) \ $(CONFIG_MCUPM_FIRMWARE) \ + $(CONFIG_PI_IMG_FIRMWARE) \ $(CONFIG_SSPM_FIRMWARE) \ $(CONFIG_SPM_FIRMWARE) diff --git a/src/soc/mediatek/mt8196/include/soc/pi_image.h b/src/soc/mediatek/mt8196/include/soc/pi_image.h new file mode 100644 index 0000000..74f8ebe --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/pi_image.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ +#define __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ + +#include <commonlib/bsd/helpers.h> +#include <soc/mcu_common.h> + +#define PI_IMAGE_CSRAM 0x00120000 +#define PI_IMAGE_CSRAM_SIZE (16 * KiB) + +size_t pi_image_load(void **buffer); + +#endif /* __SOC_MEDIATEK_MT8196_PI_IMAGE_H__ */ diff --git a/src/soc/mediatek/mt8196/pi_image.c b/src/soc/mediatek/mt8196/pi_image.c new file mode 100644 index 0000000..d1e60e0 --- /dev/null +++ b/src/soc/mediatek/mt8196/pi_image.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <arch/cache.h> +#include <assert.h> +#include <soc/mcu_common.h> +#include <soc/pi_image.h> +#include <soc/symbols.h> +#include <string.h> +#include <sys/types.h> + +static struct mtk_mcu pi_image = { + .firmware_name = CONFIG_PI_IMG_FIRMWARE +}; + +size_t pi_image_load(void **buffer) +{ + *buffer = NULL; + pi_image.load_buffer = _dram_dma; + pi_image.buffer_size = REGION_SIZE(dram_dma); + + if (mtk_init_mcu(&pi_image)) + die("%s() failed\n", __func__); + + *buffer = pi_image.load_buffer; + return pi_image.run_size; +} diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 8aca958..2d32bc3 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -11,6 +11,7 @@ #include <soc/mt6685.h> #include <soc/mtk_fsp.h> #include <soc/pcie.h> +#include <soc/pi_image.h> #include <soc/sspm.h> #include <soc/storage.h> #include <soc/symbols.h> @@ -34,11 +35,26 @@ ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); } +static void add_pi_image_params(void) +{ + void *pi_image; + size_t pi_image_size; + pi_image_size = pi_image_load(&pi_image); + + void *csram = (void *)PI_IMAGE_CSRAM; + size_t csram_size = PI_IMAGE_CSRAM_SIZE; + + mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG, pi_image_size, pi_image); + mtk_fsp_add_param(FSP_PARAM_TYPE_PI_IMG_CSRAM, csram_size, csram); +} + static void soc_init(struct device *dev) { - mtk_fsp_init(RAMSTAGE_SOC_INIT); uint32_t storage_type = mainboard_get_storage_type(); + + mtk_fsp_init(RAMSTAGE_SOC_INIT); mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type); + add_pi_image_params(); mtk_fsp_load_and_run(); mtk_mmu_disable_l2c_sram(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9 Gerrit-Change-Number: 86161 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/mediatek/common: Update fsp_status enum type
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86160?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Update fsp_status enum type ...................................................................... soc/mediatek/common: Update fsp_status enum type Sync the enum values from mtk-fsp private repo. TEST=build pass. BUG=b:373797027 Change-Id: I8a1cb107f1ff8a65962997e861e8e670cd9582a2 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86160 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/include/soc/mtk_fsp_common.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h index 99453ba..29e7ed9 100644 --- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -12,6 +12,10 @@ enum fsp_status { FSP_STATUS_SUCCESS = 0, FSP_STATUS_INVALID_VERSION, + FSP_STATUS_INVALID_PHASE, + FSP_STATUS_PARAM_NOT_FOUND, + FSP_STATUS_PARAM_INVALID_SIZE, + FSP_STATUS_INVALID_STORAGE, }; enum fsp_phase { -- To view, visit https://review.coreboot.org/c/coreboot/+/86160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a1cb107f1ff8a65962997e861e8e670cd9582a2 Gerrit-Change-Number: 86160 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/commmon: Set mcupm mcufw_reserved region to non-cacheable
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86159?usp=email ) Change subject: soc/mediatek/commmon: Set mcupm mcufw_reserved region to non-cacheable ...................................................................... soc/mediatek/commmon: Set mcupm mcufw_reserved region to non-cacheable Set mcufw_reserved region to non-cacheable and remove cache operation in dvfs.c. TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8196/dvfs.c 3 files changed, 7 insertions(+), 3 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h index f33d19a..3391467 100644 --- a/src/soc/mediatek/common/include/soc/symbols.h +++ b/src/soc/mediatek/common/include/soc/symbols.h @@ -9,6 +9,6 @@ DECLARE_REGION(resv_mem_optee) DECLARE_REGION(resv_mem_gpu) DECLARE_REGION(resv_mem_gpueb) -DECLARE_REGION(mcufw_reserved) +DECLARE_OPTIONAL_REGION(mcufw_reserved) #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index be216f6..5471af2 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -4,6 +4,7 @@ #include <symbols.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h> __weak void mtk_soc_after_dram(void) { /* do nothing */ } @@ -35,6 +36,11 @@ mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), SECURE_UNCACHED_MEM); + /* Set mcufw_reserved to non-cacheable */ + if (REGION_SIZE(mcufw_reserved) != 0) + mmu_config_range(_mcufw_reserved, REGION_SIZE(mcufw_reserved), + SECURE_UNCACHED_MEM); + mmu_enable(); } diff --git a/src/soc/mediatek/mt8196/dvfs.c b/src/soc/mediatek/mt8196/dvfs.c index da0fdaa..255f95e 100644 --- a/src/soc/mediatek/mt8196/dvfs.c +++ b/src/soc/mediatek/mt8196/dvfs.c @@ -12,6 +12,4 @@ write32p(CSRAM_BASE + 0x8, 0x55AA55AA); write32p(CSRAM_BASE + 0xC, val); - - dcache_clean_invalidate_by_mva((void *)CSRAM_BASE, CACHE_LINE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Gerrit-Change-Number: 86159 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Correct SPM firmware file suffix to .bin
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86156?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Correct SPM firmware file suffix to .bin ...................................................................... soc/mediatek/mt8196: Correct SPM firmware file suffix to .bin Correct SPM firmware file suffix from .pm to .bin in Kconfig. coreboot log: mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 3 msecs (30114 bytes) SPM: spm_init done in 3 msecs, spm pc = 0x1430 TEST=Build pass, boot successful. BUG=b:348147674 Change-Id: I053e08c9665d434e4fc9a01bca52101218b2c634 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86156 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 6d7ea68..fe89288 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -47,7 +47,7 @@ config SPM_FIRMWARE string - default "spm_firmware.pm" + default "spm_firmware.bin" help The file name of the MediaTek SPM firmware. -- To view, visit https://review.coreboot.org/c/coreboot/+/86156?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I053e08c9665d434e4fc9a01bca52101218b2c634 Gerrit-Change-Number: 86156 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 23:40:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/erying/tgl: Drop specifying which timers to use
by Angel Pons (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Alicja Michalska, Matt DeVillier. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86093?usp=email ) Change subject: mb/erying/tgl: Drop specifying which timers to use ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86093/comment/62b245ff_c01f3873?us… : PS2, Line 1: Parent: 9dee482a (mb/google/nissa/var/telith: Configure Acoustic noise mitigation) > Right, sorry, two separate things. This one is about recovering from "sleep". […] Ah, I see. Makes sense, thank you! Could you please add this information to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/86093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e0ac1d289447c292a49111251d321c951078e2 Gerrit-Change-Number: 86093 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 23:40:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 27 Jan 2025 23:40:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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