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[XS] Change in coreboot[main]: fatcat-ish: disable UART0 RX
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N. Subrata Banik has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email ) Change subject: fatcat-ish: disable UART0 RX ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/86005/comment/43eb3a30_b6ad1475?us… : PS2, Line 421: /* GPP_D05: NC */ : PAD_NC(GPP_D05, NONE) we might need to add this code inside FPS enable ? https://review.coreboot.org/c/coreboot/+/86005/comment/5e454a83_1e1f25e9?us… : PS2, Line 432: /* GPP_D05: ISH_UART0_RXD */ : PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), isn't it impact ISH UART functionality ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 06:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add P8Z77-V LE PLUS variant
by Keith Hui (Code Review) 28 Jan '25

28 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86172?usp=email ) Change subject: mb/asus/p8x7x-series: Add P8Z77-V LE PLUS variant ...................................................................... mb/asus/p8x7x-series: Add P8Z77-V LE PLUS variant Based on a mix of existing P8x7x series boards, boardview, vendor firmware dumps, and hardware testing. Working: - Boots to SeaBIOS 1.16.3 and edk2/mrchromebox/uefipayload_2501 - Serial port - All USB2 ports - All back panel USB3 ports - Z77 SATA ports - Integrated graphics thru all ports with libgfxinit - RTL8111F LAN - Analog 7.1 audio out the back panel jacks - Digital audio - PCIe x16 with nVidia 8800GT GPU - PCIe x1 slots - PCI slots - Hardware monitoring and fan control - S3 suspend Untested: - Internal USB3 header - Front audio panel Not working: - Programming LAN MAC address (yet) - Marvell SATA ports Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p8z77-v_le_plus.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb 13 files changed, 943 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/86172/1 diff --git a/Documentation/mainboard/asus/p8z77-v_le_plus.md b/Documentation/mainboard/asus/p8z77-v_le_plus.md new file mode 100644 index 0000000..382c309 --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-v_le_plus.md @@ -0,0 +1,230 @@ +# ASUS P8Z77-V LE PLUS + +This page describes how to run coreboot on the [ASUS P8Z77-V LE PLUS]. + +## Flashing coreboot + +```{eval-rst} ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +### How to flash + +The main SPI flash cannot be written because the vendor firmware disables BIOSWE +and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external +programmer is required. You must flash standalone, flashing in-circuit doesn't +work. The flash chip is socketed, so it's easy to remove and reflash. + +See page 2-2 of user's manual for flash chip location. + +Before flashing coreboot for the first time, enter vendor UEFI setup and set PCIEX16_3 +(black) slot bandwidth to x2 and reboot once. If not done, the two PCIe x1 slots will +be disabled. See [PCIe config] section below for details. + +## Working + +- Core i5-3570K and i7-3770K CPUs +- Corsair CMZ16GX3M2A1600C10 2x8GB memory kit +- SeaBIOS 1.16.3 +- edk2 mrchromebox fork uefipayload_2501 +- Kernel 6.12.7 +- All USB2 ports (mouse, keyboard) +- Z77 USB3 ports on rear (Boots Arch-based SystemRescue 11.03 off a Kingston DataTraveler 4GB) +- Z77 SATA ports (WD Blue SA510, Liteon LH-20A1L) +- Asmedia USB3 ports on rear (Kingston DataTraveler G4 8GB; can even be used for booting) +- nVidia 8800GT GPU in PCIEX16_1 slot running x16 +- PCI slots (Sound Blaster Live! CT4830 detected, not function tested) +- Gigabit Ethernet (RTL8111F) +- CPU Temp sensors and hardware monitor (see [Known issues]) +- Integrated graphics with libgfxinit and VBT + (HDMI, VGA, DVI-D, DisplayPort tested and working) +- Both PCIe x1 slots when properly configured (see [How to flash] above and [PCIe config]; + Atheros 928x miniPCIe Wifi on adapter & MSI Herald-BE Wifi7 adapter) +- Serial port +- PS/2 keyboard +- Analog 7.1 audio out the 3.5mm jacks on rear panel +- Digital audio out (Optical, internal SPDIF header, HDMI, DisplayPort) + + Although a `spdif_dest` CMOS option is provided for feature parity with vendor firmware, + it doesn't seem to matter and digital audio out is available through all known ports. + It does, however, change how the ports are presented to the OS. + +- S3 suspend from Linux + +## Known issues + +- RTL8111F here has no EEPROM for vital product data such as MAC address, which is also not + being properly programmed. You may need to fuse your MAC address with [rtnicpg] instead. +- For 7.1 analog audio to work, at least the front channel (green jack) must be connected. + +## Untested + +- Internal Z77 USB3 header +- PS/2 mouse (probably requires a patch currently under review) +- Hotplug of Z77 SATA ports +- Wake-on-LAN +- Front audio panel +- EHCI debugging + +## Not working + +- Asmedia USB 3.0 battery charging support (for USB 3 ports on the LAN stack) +- USB Charger+ (When the bottom USB 3 port on the eSATA stack remains powered while the + rest of the system is off. This is controlled by the AI1314 chip also responsible for + BIOS flashback.) +- Marvell SATA ports are brought up in IDE mode, pata_marvell driver is loaded, + but are effectively unusable. + +## PCIe config +On vendor firmware, the black PCIEX16_3 slot can be configured as x2 or x4. +If set for x4, PCIEX1_1 and PCIEX1_2 are disabled. + +Changing this requires manipulating a PCH GPIO line and a soft strap in the flash chip's +descriptor section, which is read-only at runtime. How coreboot can manage this in software is +to be determined. Until then support for this feature is incomplete - coreboot programs the +GPIO to match the soft strap. + +## Hardware monitoring and fan speed control + +Although all fan ports are 4-pin for PWM fans, only CPU_FAN has actual PWM control; +all other fan speed control is by voltage only. + +Write 1 into `/sys/class/hwmon/hwmon1/pwm1_mode` to enable CHA_FAN1 control, otherwise it +runs at full speed. + +`pwm5` is not connected and should be ignored. + +These are the sensors.conf settings for this board: + +```bash +label fan1 "CHA_FAN1" +label fan2 "CPU_FAN" +label fan3 "CHA_FAN2" +label fan4 "CHA_FAN3" +ignore fan5 +label in1 "+12V" +label in4 "+5V" +compute in1 @*12, @/12 +compute in4 @*5, @/5 +set temp1_type 4 +set temp2_type 4 +``` + +## Extra onboard switches and LEDs + +- `BIOS_FLBK`: + Vendor firmware uses this button to facilitate a simple update mechanism + via a USB drive plugged into the bottom USB port of the USB/ESATA6G stack. + It connects to the proprietary AI1314 controller, along with `FLBK_LED`. + +- `MemOK!`: + OEM firmware uses this button for memory tuning related to overclocking. + It connects to pin 74 of super I/O. + +- `DRAM_LED` lights up when there is a memory problem or when vendor MemOK! feature is + operating. Connects to GP07 line of super I/O. coreboot lights it up during memory init + similar to vendor firmware. + +- `EPU`: When enabled, lights up `EPU_LED` and takes PCH GPIO44 low. +- `TPU`: When enabled, lights up `TPU_LED` and takes PCH GPIO45 low. + + `EPU` and `TPU` are cues to vendor firmware to enable two embedded controllers for + overclocking features. coreboot is not yet able to make use of these two signals. + +- `SB_PWR` lights up whenever board is receiving power. It's all hardware + and does not concern coreboot. + +- `CHASSIS` is an undocumented 2-pin header next to the front panel connector block. It + is Z77's intruder detection input. Switches connected here should close the contact + if case is opened. It's up to software to use it; coreboot doesn't. + +## Extra exposed GPIOs at `TB_HEADER` + +A number of GPIO lines are broken out to `TB_HEADER` in support of the ThunderboltEX +adapter, which never took off. Now it's yours to play with. Additional programming may be +required such as to enable GPIO by I/O for maximum effect. + +This may be safely ignored for most normal uses. + +**Be careful not to apply too high a voltage to these pins!** And do not touch the two pins +labeled "NOT A GPIO". + + +Pinout: +``` + +---+---+---+---+---+ + | 2 | 4 | 5 | 7 | 9 | + +---+---+---+---+---+ + | 1 | 3 | | 6 | 8 | + +---+---+---+---+---+ +``` + +```{eval-rst} ++-----+-----------------------+----------+--------+ +| Pin | Name | Source | GPIO # | ++=====+=======================+==========+========+ +| 1 | S_DP_DDC_CLK_TO_TB | **NOT A GPIO** | ++-----+-----------------------+----------+--------+ +| 2 | TB_GPIO_6 `#` | NCT6779D | 14 | ++-----+-----------------------+----------+--------+ +| 3 | S_DP_DDC_DATA_TO_TB | **NOT A GPIO** | ++-----+-----------------------+----------+--------+ +| 4 | TB_GPIO_7 `#` | NCT6779D | 13 | ++-----+-----------------------+----------+--------+ +| 5 | TB_FWUPDATE | NCT6779D | 11 | ++-----+-----------------------+----------+--------+ +| 6 | TB_DEV_HPD `#` | Z77 | 0 | ++-----+-----------------------+----------+--------+ +| 7 | TB_GO2SX | NCT6779D | 17 | ++-----+-----------------------+----------+--------+ +| 8 | TB_GO2SX#_ACK `#` | NCT6779D | 16 | ++-----+-----------------------+----------+--------+ +| 9 | Not connected | ++-----+-------------------------------------------+ +``` + +Lines marked `#` have pulldowns. + + +## Technology + +```{eval-rst} ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | TPU (ENE KB3722), AI1314 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8Z77-V LE PLUS]: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom +[rtnicpg]: https://github.com/redchenjs/rtnicpg diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f9f9048..9d1a6ed 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -53,6 +53,7 @@ P8Z77-M <asus/p8z77-m.md> P8Z77-M Pro <asus/p8z77-m_pro.md> P8Z77-V <asus/p8z77-v.md> +P8Z77-V LE PLUS <asus/p8z77-v_le_plus.md> wifigo_v1 <asus/wifigo_v1.md> ``` diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index d555cc6..2beca1d 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -58,6 +58,16 @@ select SUPERIO_NUVOTON_NCT6779D select SUPERIO_NUVOTON_COMMON_COM_A +config BOARD_ASUS_P8Z77_V_LE_PLUS + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_COMMON_COM_A + select USE_NATIVE_RAMINIT + select POWER_LED_USES_GPIO8 + select HAVE_SHARED_PS2_PORT + if BOARD_ASUS_P8X7X_SERIES config POWER_LED_USES_GPIO8 @@ -75,6 +85,7 @@ default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V default "p8z77-m" if BOARD_ASUS_P8Z77_M + default "p8z77-v_le_plus" if BOARD_ASUS_P8Z77_V_LE_PLUS config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -83,6 +94,7 @@ default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V default "P8Z77-M" if BOARD_ASUS_P8Z77_M + default "P8Z77-V LE PLUS" if BOARD_ASUS_P8Z77_V_LE_PLUS config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index a5598ca..c27e008 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -17,3 +17,6 @@ config BOARD_ASUS_P8Z77_M bool "P8Z77-M" + +config BOARD_ASUS_P8Z77_V_LE_PLUS + bool "P8Z77-V LE PLUS" diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt new file mode 100644 index 0000000..53bbee1 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default new file mode 100644 index 0000000..ae789bb --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.default @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +gfx_uma_size=64M +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M +audio_panel_type=HDA +spdif_dest=SPDIF_OUT +pciex16_3_bandwidth=x2 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout new file mode 100644 index 0000000..07b2a8c --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/cmos.layout @@ -0,0 +1,102 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: mainboard +425 1 e 9 audio_panel_type +426 1 e 10 spdif_dest +427 1 e 11 pciex16_3_bandwidth +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# audio_panel_type +9 0 HDA +9 1 AC97 + +# spdif_dest +10 0 SPDIF_OUT +10 1 HDMI + +# pciex16_3_bandwidth +11 0 x2 +11 1 x4 + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt new file mode 100644 index 0000000..a89353d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c new file mode 100644 index 0000000..eb0b431 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> +#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <console/console.h> +#include <option.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V) + +enum pciex16_3_bandwidth { + PCIEX16_3_X2 = 0, + PCIEX16_3_X4 = 1 +}; + +void mainboard_late_rcba_config(void) +{ + /* This is called after raminit. We turn off DRAM_LED here. */ + nuvoton_pnp_enter_conf_state(GPIO0_DEV); + pnp_set_logical_device(GPIO0_DEV); + pnp_write_config(GPIO0_DEV, 0xe1, 0x80); + nuvoton_pnp_exit_conf_state(GPIO0_DEV); + + DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); + DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); + DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQH, PIRQF, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D22IR, PIRQF, PIRQD, PIRQC, PIRQB); +} + +void bootblock_mainboard_init(void) +{ + int gp46 = 0; + + /* PCHSTRP9[PCIEPCS1] soft strap (reflected here) tells us how PCIe lanes 1-4 are + * configured. + * + * GPIO46 controls one ASM1440 switch that routes PCH PCIe lanes 3 & 4 as follows: + * 0 = PCIEX1_1 and PCIEX1_2 respectively (pulled low on board) + * 1 = PCIEX16_3 + */ + u8 old_pciepcs1 = RCBA32(RPC) & 0x3; + u8 pciepcs1 = old_pciepcs1; + + switch (pciepcs1) { + case 1: /* 1 x2, 3/4 x1 */ + break; + case 3: /* 1 x4 */ + gp46 = 1; + break; + default: + printk(BIOS_ERR, "PCH PCIe lane configuration 0x%x is invalid!\n", pciepcs1); + } + + /* Match GPIO to soft strap. */ + set_gpio(46, gp46); + + unsigned int pciex16_bandwidth = get_uint_option("pciex16_3_bandwidth", PCIEX16_3_X2); + pciepcs1 = (pciex16_bandwidth == PCIEX16_3_X4) ? 3 : 1; + if (pciepcs1 != old_pciepcs1) { + /* TODO: PCHSTRP9 needs to change. Flash it to IFD and force a total reset. */ + } + + /* + * TODO: Put PCIe root port 6 into subtractive decode and have it accept I/O + * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 + * bridge to this port, to receive POST codes. + */ +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + pnp_write_config(GLOBAL_DEV, 0x27, 0x10); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + /* Turn on DRAM_LED. If raminit dies, this would remain on and we know + * we have a problem. We turn it off in ramstage. */ + pnp_set_logical_device(GPIO0_DEV); + pnp_write_config(GPIO0_DEV, 0x30, 0x02); + pnp_write_config(GPIO0_DEV, 0xe0, 0x7f); + pnp_write_config(GPIO0_DEV, 0xe1, 0x00); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads new file mode 100644 index 0000000..e6b0407 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c new file mode 100644 index 0000000..c7581ac --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, /* SMI# of ASM1042 USB3 */ + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, /* PCIEX16_3 card presence, active low */ + .gpio8 = GPIO_MODE_GPIO, /* Power LED */ + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, /* ME_UNLOCK (Set high to unlock SPI descriptor) */ + .gpio28 = GPIO_MODE_GPIO, /* S_IVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /* EC_SPI_WP# */ + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, /* AI1314 BCS1 */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio27 = GPIO_RESET_RSMRST +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, /* EPU switch, active low */ + .gpio45 = GPIO_MODE_GPIO, /* TPU switch, active low */ + .gpio46 = GPIO_MODE_GPIO, /* QSWU1 (High = PCH PCIe lanes 3/4 goes to PCIEX16_3) */ + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, /* AI1314 BCS0 */ + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio46 = GPIO_LEVEL_LOW, /* Needs to be set at runtime */ + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio46 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, /* RTL8111 ISOLATE# */ + .gpio69 = GPIO_MODE_GPIO, /* A BIOS flashback signal */ + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, /* WP# of main SPI flash chip */ + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c new file mode 100644 index 0000000..5bfa977 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/hda_verb.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <option.h> + +/* Shorthands */ +#define AZALIA_PIN_REAR(dev, color, misc, association, sequence) \ +AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_REAR, dev, AZALIA_STEREO_MONO_1_8, \ + color, misc, association, sequence) +#define AZALIA_PIN_FRONT(dev, color, misc, association, sequence) \ +AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_FRONT, dev, AZALIA_STEREO_MONO_1_8, \ + color, misc, association, sequence) + +const u32 cim_verb_data[] = { + 0x10ec0889, /* Realtek ALC889 */ + 0x1043841a, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043841a), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0)), /* SPDIF out 2, 0x99430130 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_REAR( + AZALIA_LINE_OUT, + AZALIA_GREEN, + 0, + 1, 0)), /* 0x01014010 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_REAR( + AZALIA_LINE_OUT, + AZALIA_BLACK, + 0, + 1, 2)), /* 0x01011012 */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_REAR( + AZALIA_LINE_OUT, + AZALIA_ORANGE, + 0, + 1, 1)), /* 0x01016011 */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_REAR( + AZALIA_LINE_OUT, + AZALIA_GREY, + 0, + 1, 4)), /* 0x01012014 */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_REAR( + AZALIA_MIC_IN, + AZALIA_PINK, + 8, + 5, 0)), /* 0x01a19850 */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_FRONT( + AZALIA_MIC_IN, + AZALIA_PINK, + 0xc, + 6, 0)), /* 0x02a19c60 */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_REAR( + AZALIA_LINE_IN, + AZALIA_BLUE, + 0, + 5, 15)), /* 0x0181305f */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_FRONT( + AZALIA_HP_OUT, + AZALIA_GREEN, + 0xc, + 2, 0)), /* 0x02214c20),*/ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), /* Beep */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_ORANGE, + AZALIA_NO_JACK_PRESENCE_DETECT, + 4, 0)), /* 0x01456140 */ + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + 0x80862806, /* Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; + +enum e_spdif2_dest { + SPDIF2_SPDIF_OUT = 0, + SPDIF2_HDMI +}; + +enum e_aafp { + AAFP_HDA = 0, + AAFP_AC97 +}; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + /* + * With vendor firmware, if audio front panel type is set as AC97, line out 2 + * (0x1b) and mic 2 (0x19) pins of ALC889 are configured differently. + * + * The differences are all in the "Misc" fields of configuration defaults (in byte 2) + * as shown below. Datasheet did not offer details on what those bits + * (listed as reserved in HDA spec) are, so we'll have to take their word for it. + * + * Pin | 0x19 | 0x1b + * -----+------+----- + * HDA | 1100 | 1100 + * AC97 | 1001 | 0001 + */ + const u32 front_aafp_verbs[] = { + AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99), + AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41) + }; + + /* If user chooses to have digital audio out 2 to go on the HDMI port, + * reprogram this pin as such: + * + * AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + * AZALIA_JACK, + * AZALIA_DIGITAL_DISPLAY, + * AZALIA_DIGITAL_OTHER_OUT, + * AZALIA_OTHER_DIGITAL, + * AZALIA_BLACK, + * AZALIA_NO_JACK_PRESENCE_DETECT, + * 3, 0)) + * + * Coded this way because we don't need to reprogram byte 0. + */ + const u32 spdif_to_hdmi_verbs[] = { + AZALIA_VERB_12B(0, 0x11, 0x71f, 0x18), + AZALIA_VERB_12B(0, 0x11, 0x71e, 0x56), + AZALIA_VERB_12B(0, 0x11, 0x71d, 0x11) + }; + + if (viddid == 0x10ec0889) { + if (get_uint_option("audio_panel_type", AAFP_HDA) == AAFP_AC97) { + azalia_program_verb_table(base, front_aafp_verbs, + ARRAY_SIZE(front_aafp_verbs)); + } + if (get_uint_option("spdif_dest", SPDIF2_SPDIF_OUT) == SPDIF2_HDMI) { + azalia_program_verb_table(base, spdif_to_hdmi_verbs, + ARRAY_SIZE(spdif_to_hdmi_verbs)); + } + } +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb new file mode 100644 index 0000000..3002648 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb @@ -0,0 +1,84 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + device ref peg11 on end # PCIEX_16_2 + device ref peg12 hidden end # Board cannot do 8/4/4 split + device ref dev4 hidden end + device ref peg60 hidden end + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 2, 0 }, + { 1, 8, 0 }, + { 1, 8, 1 }, + { 1, 8, 1 }, + { 1, 9, 2 }, + { 1, 9, 2 }, + { 1, 0xa53, 3 }, + { 1, 0xa53, 3 }, + { 1, 0xa53, 4 }, + { 1, 0xa53, 4 }, + { 1, 0xa53, 6 }, + { 1, 0xa53, 5 }, + { 1, 0xa53, 5 }, + { 1, 0xa53, 6 } + }" + register "gen1_dec" = "0x000c0291" # NCT6779 HWM + register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC + + device ref pcie_rp1 on end # PCIEX_16_3 (electrical x2 or x4) + device ref pcie_rp3 on end # PCIEX_1_1 + device ref pcie_rp4 on end # PCIEX_1_2 + device ref pcie_rp5 on # RTL8111 LAN + chip drivers/net + register "customized_leds" = "0x482" + device pci 00.0 on end + end + end + device ref pcie_rp6 on end # ASM1083 PCI bridge + device ref pcie_rp7 on end # Marvell 88SE9120 ESATA6G + device ref pcie_rp8 on end # ASM1042 USB3 + + device ref lpc on + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.509 on end # GPIO5 all in + device pnp 2e.a on # ACPI + drq 0xe7 = 0x11 + drq 0xf2 = 0x5d # Enable PME + end + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x290 + io 0x62 = 0 + irq 0x70 = 0 + drq 0xe4 = 0xf9 # Use GP50/52/55 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/86172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50 Gerrit-Change-Number: 86172 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED
by Keith Hui (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Bill XIE, Paul Menzel. Hello Bill XIE, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82556?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED ...................................................................... mb/asus/p8x7x-series: Mark variants using GPIO8 for power LED All boards in the family have the negative leg of power LED linked to a PCH GPIO pin, either GPIO 27 or 8. After examining their boardviews, mark p8h77-v and p8z77-v_lx2 variants through Kconfig as using GPIO8 for power LED. Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82556/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30 Gerrit-Change-Number: 82556 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Elyes Haouas, Karthik Ramasubramanian, Raul Rangel. Jon Murphy has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Latest patch sets were uploaded in place to force copybot to evaluate the verified tag again. […] Misunderstood, the vote was copied but the job was still triggered again. -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 Jan 2025 03:54:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com>

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Elyes Haouas, Karthik Ramasubramanian, Raul Rangel. Jon Murphy has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Latest patch sets were uploaded in place to force copybot to evaluate the verified tag again. Is there another way to force this? -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 Jan 2025 03:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Elyes Haouas, Jon Murphy, Karthik Ramasubramanian, Raul Rangel. Hello Karthik Ramasubramanian, Martin L Roth, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86171?usp=email to look at the new patch set (#4). Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... util/crossgcc/buildgcc: Add riscv64-elf to targets All of the other targets support invoking the build with the full target arch name. RISC does not. Update the script to allow riscv64-elf to invoke the build the same way that riscv-elf does to minimize name mangling and exceptions needed for tooling surrounding the architecture name in paths. Leave riscv-elf in tact as an option so we don't break anyone else. BUG=None TEST=./util/crossgcc/buildgcc --platform riscv64-elf Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86171/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Elyes Haouas, Karthik Ramasubramanian, Martin L Roth, Raul Rangel. Jon Murphy has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86171/comment/770c3d1d_f56ec133?us… : PS1, Line 19: > Missing: Signed-off-by: Jon Murphy <jpmurphy@google. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 Jan 2025 02:43:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin L Roth, Raul Rangel. Hello Karthik Ramasubramanian, Martin L Roth, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86171?usp=email to look at the new patch set (#2). Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... util/crossgcc/buildgcc: Add riscv64-elf to targets All of the other targets support invoking the build with the full target arch name. RISC does not. Update the script to allow riscv64-elf to invoke the build the same way that riscv-elf does to minimize name mangling and exceptions for the architecture name in paths. Leave riscv-elf in tact as an option so we don't break anyone else. BUG=None TEST=./util/crossgcc/buildgcc --platform riscv64-elf Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86171/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Elyes Haouas (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin L Roth, Raul Rangel. Elyes Haouas has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86171/comment/dfd0a0dc_a247f125?us… : PS1, Line 19: Missing: Signed-off-by: Jon Murphy <jpmurphy(a)google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 02:31:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Disable UFS controller on every boot
by Bob Moragues (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Bob Moragues has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: soc/intel/alderlake/romstage: Disable UFS controller on every boot ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 01:49:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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