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Change subject: mb/google/rauru: Add alc5650 support
......................................................................
mb/google/rauru: Add alc5650 support
Configure ALC5650 for hylia to support beep sound in depthcharge.
BRANCH=rauru
BUG=b:383376419
TEST=Verify devbeep in depthcharge console
Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988
Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/rauru/chromeos.c
M src/mainboard/google/rauru/devicetree.cb
M src/mainboard/google/rauru/gpio.h
M src/mainboard/google/rauru/mainboard.c
4 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/85858/3
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/google/rauru: Add alc5650 support
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85858/comment/1299591e_1494f339?us… :
PS2, Line 9: depthcharge
the payload
File src/mainboard/google/rauru/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85858/comment/e66be4c3_3e0a1256?us… :
PS2, Line 21: i2s
> Could you also send a separate patch and rename this to `configure_tas2563` ?
I'm fine with doing that in this patch, as it's only straightforward refactoring.
https://review.coreboot.org/c/coreboot/+/85858/comment/6af344a4_b4d3151e?us… :
PS2, Line 33: {
Should we add `/* Switch to normal mode */` similar to the code above?
https://review.coreboot.org/c/coreboot/+/85858/comment/b83ccb03_19f27710?us… :
PS2, Line 34: write32p(AFE_SE_SECURE_CON1, 0x0);
A blank line below.
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/ebg/soc_xhci.c:
https://review.coreboot.org/c/coreboot/+/85809/comment/94b1eca3_9460a095?us… :
PS3, Line 21:
> When get_xhci_bar is called, the initial mapping is assumed to be mapped by FSP and not coreboot her […]
PCI resource allocation is done by FSP and it assignes BAR in high MMIO while coreboot defaults to low MMIO for most BARs.
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Change subject: soc/mediatek/mt8196: Correct MT6363 buck5 enable API
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85838/comment/05fdf96c_98182b85?us… :
PS1, Line 7: Correct MT6363 buck5 enable API
> Fix MT6363 buck5 enablement API
`Fix MT6363 buck5 enablement` (because the API (interface) isn't wrong)
https://review.coreboot.org/c/coreboot/+/85838/comment/8edcf854_80b9e06d?us… :
PS1, Line 9: MT6363 buck5 is not used in rauru/navi. Fixed the incorrect mask and
: offset in the enable API.
> The MT6363 buck5 API's mask and offset settings were incorrect, preventing the buck from being disab […]
Modify a few words:
```
The MT6363 buck5 API's mask and shift settings are incorrect, preventing the buck from being disabled. Resolve the issue by correcting these two values.
```
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Change subject: soc/mediatek/mt8196: Add delay in pmif_spmi.c
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85799/comment/ccf31407_8c278fcd?us… :
PS2, Line 7: Add delay in pmif_spmi.c
> The 500 microseconds delay is implemented to ensure that the two fields, inf_en and arb_en of the PM […]
Thanks for the explanation. In that case, please change the commit subject to "Delay 0.5ms after enabling ...".
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Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
Patch Set 8:
(2 comments)
File src/soc/mediatek/mt8196/gpueb.c:
https://review.coreboot.org/c/coreboot/+/85654/comment/da80b075_68592940?us… :
PS7, Line 204: Failed to parse load buffer
> Buffer size too small
Done
https://review.coreboot.org/c/coreboot/+/85654/comment/4c969329_397d8a1e?us… :
PS7, Line 233: {
> remove
Done
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Hello Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85654?usp=email
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Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek/mt8196: Add GPUEB support
......................................................................
soc/mediatek/mt8196: Add GPUEB support
GPUEB is a micro-processor used for GPU power management. It is also
responsible for controlling GPU DVFS and GPU thermal throttling. This
gpueb load flow adds 47ms to the boot time.
coreboot log:
CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374
Loaded (and reset) gpueb_fw.img in 47 msecs.
TEST=Boot ok
BUG=b:317009620
Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com>
Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2
---
M src/soc/mediatek/common/include/soc/symbols.h
M src/soc/mediatek/mt8196/Kconfig
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/gpueb.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/gpueb.h
A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h
M src/soc/mediatek/mt8196/include/soc/memlayout.ld
M src/soc/mediatek/mt8196/soc.c
9 files changed, 608 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/8
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Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363
......................................................................
Patch Set 2: Code-Review+2
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