coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/starlabs/starlite: Set Touch Panel Reset (GPP_F17) to host owned
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85699?usp=email ) Change subject: mb/starlabs/starlite: Set Touch Panel Reset (GPP_F17) to host owned ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e1249addcfb831deee81024a37a867c79b1b0f9 Gerrit-Change-Number: 85699 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 22:12:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/*: Select TPM2 so PPI is generated
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85697?usp=email ) Change subject: mb/starlabs/*: Select TPM2 so PPI is generated ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85697?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d6633291ba635c5a2f7eb36e64a327d9a4da5cf Gerrit-Change-Number: 85697 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 22:12:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for CPU Root Ports
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email ) Change subject: intel/common/rtd3: Allow emitting PSD0 Method for CPU Root Ports ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia34cc1f9099ca88fa16a83174ec90ca14f43ab56 Gerrit-Change-Number: 85696 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 22:12:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add SSDT entry for volume keys
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85695?usp=email ) Change subject: mb/starlabs/starlite_adl: Add SSDT entry for volume keys ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80491559de50d72bf1ff97fd30c1a74e6b0f7a6 Gerrit-Change-Number: 85695 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 22:11:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Hero (Haswell)
by Jan Philipp Groß (Code Review) 06 Jan '25

06 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85872?usp=email ) Change subject: mb/asus: Add Maximus VI Hero (Haswell) ...................................................................... mb/asus: Add Maximus VI Hero (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3 DIMM slots - HDMI-Out Port - RJ-45 Gigabit LAN Port - All four back panel USB 2.0 Ports - All four back panel USB 3.0 Ports - USB 2.0 Header - USB 3.0 Header - All six SATA3 6.0 Gb/s connectors by Intel - PCI Express 3.0/2.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - S3 suspend and resume - Both SATA3 6.0 GB/s connectors by ASMedia (fix will soon be merged) - Various LED effects (purely cosmetical) Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asus/maximus_vi_hero/Kconfig A src/mainboard/asus/maximus_vi_hero/Kconfig.name A src/mainboard/asus/maximus_vi_hero/Makefile.mk A src/mainboard/asus/maximus_vi_hero/acpi/ec.asl A src/mainboard/asus/maximus_vi_hero/acpi/platform.asl A src/mainboard/asus/maximus_vi_hero/acpi/superio.asl A src/mainboard/asus/maximus_vi_hero/board_info.txt A src/mainboard/asus/maximus_vi_hero/bootblock.c A src/mainboard/asus/maximus_vi_hero/data.vbt A src/mainboard/asus/maximus_vi_hero/devicetree.cb A src/mainboard/asus/maximus_vi_hero/dsdt.asl A src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads A src/mainboard/asus/maximus_vi_hero/gpio.c A src/mainboard/asus/maximus_vi_hero/hda_verb.c A src/mainboard/asus/maximus_vi_hero/romstage.c 15 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85872/1 diff --git a/src/mainboard/asus/maximus_vi_hero/Kconfig b/src/mainboard/asus/maximus_vi_hero/Kconfig new file mode 100644 index 0000000..d7b4300 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_MAXIMUS_VI_HERO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config MAINBOARD_DIR + default "asus/maximus_vi_hero" + +config MAINBOARD_PART_NUMBER + default "Maximus VI HERO" + +config USBDEBUG_HCD_INDEX + default 2 # Lower one of the middle rear USB-2.0-Port + # and and USB-3.0-Header +endif diff --git a/src/mainboard/asus/maximus_vi_hero/Kconfig.name b/src/mainboard/asus/maximus_vi_hero/Kconfig.name new file mode 100644 index 0000000..c6cd0e6 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_MAXIMUS_VI_HERO + bool "Maximus VI HERO" diff --git a/src/mainboard/asus/maximus_vi_hero/Makefile.mk b/src/mainboard/asus/maximus_vi_hero/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl b/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl b/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl b/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl new file mode 100644 index 0000000..73fa78e --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/asus/maximus_vi_hero/board_info.txt b/src/mainboard/asus/maximus_vi_hero/board_info.txt new file mode 100644 index 0000000..2da82ea --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_VI_HERO/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asus/maximus_vi_hero/bootblock.c b/src/mainboard/asus/maximus_vi_hero/bootblock.c new file mode 100644 index 0000000..36bfb91e --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/bootblock.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) +#define GPIO_PP_OD_DEV PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x0a); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x76); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x27, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + + /* Select push-pull vs. open-drain output */ + pnp_set_logical_device(GPIO_PP_OD_DEV); + pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe); + pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x6f); + pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x7f); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/maximus_vi_hero/data.vbt b/src/mainboard/asus/maximus_vi_hero/data.vbt new file mode 100644 index 0000000..748d5f5 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/data.vbt Binary files differ diff --git a/src/mainboard/asus/maximus_vi_hero/devicetree.cb b/src/mainboard/asus/maximus_vi_hero/devicetree.cb new file mode 100644 index 0000000..ed6e6e4 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/devicetree.cb @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1043 0x8534 + end + device pci 01.0 on # PEG + subsystemid 0x1043 0x8534 + end + device pci 02.0 on # iGPU + subsystemid 0x1043 0x8534 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1043 0x8534 + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x00040069" + register "gpe0_en_1" = "0x40002046" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1043 0x8534 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1043 0x8534 + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x859f + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x8534 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1043 0x859d + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4: ASM1061 Serial ATA Controller + subsystemid 0x1043 0x8534 + end + device pci 1c.4 on # RP #5: PCIEX4_3 + end + device pci 1c.5 on # RP #6: PCIEX1_1 + subsystemid 0x1043 0x8534 + end + device pci 1c.6 on # RP #7: PCIEX1_2 + end + device pci 1c.7 on # RP #8: PCIEX1_3 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x8534 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x8534 + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0xff + irq 0xe1 = 0xff + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xff + irq 0xf1 = 0xa3 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xdf + irq 0xe1 = 0xc0 + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x10 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0xfd + irq 0xf1 = 0x06 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xfa + irq 0xf5 = 0x68 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x12 + irq 0xed = 0x01 + irq 0xf0 = 0x30 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1043 0x8534 + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x8534 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_vi_hero/dsdt.asl b/src/mainboard/asus/maximus_vi_hero/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads b/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads new file mode 100644 index 0000000..fe20619 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_vi_hero/gpio.c b/src/mainboard/asus/maximus_vi_hero/gpio.c new file mode 100644 index 0000000..5982916 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/gpio.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_vi_hero/hda_verb.c b/src/mainboard/asus/maximus_vi_hero/hda_verb.c new file mode 100644 index 0000000..49ec798 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x1043859d, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043859d), + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1e, 0x01456140), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_vi_hero/romstage.c b/src/mainboard/asus/maximus_vi_hero/romstage.c new file mode 100644 index 0000000..8986770 --- /dev/null +++ b/src/mainboard/asus/maximus_vi_hero/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Gerrit-Change-Number: 85872 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Declare all DDI interfaces
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Paul Menzel, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85693?usp=email ) Change subject: mb/starlabs/*: Declare all DDI interfaces ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f736761bcc177afebb98eb2f612b089bc6f13a4 Gerrit-Change-Number: 85693 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 06 Jan 2025 21:58:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Unify WiFi driver settings
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85692?usp=email ) Change subject: mb/starlabs/*: Unify WiFi driver settings ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0fd6b3dd67583842e4520679b7a9c3ab9f433c4 Gerrit-Change-Number: 85692 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 21:52:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/*: Configure GPIO UPDs for eSPI
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85691?usp=email ) Change subject: mb/starlabs/*: Configure GPIO UPDs for eSPI ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85691/comment/65c98029_6a24ff6a?us… : PS6, Line 9: FSP defaults to using pins that are used for LPC; given that : coreboot and these boards only supports eSPI, set these pins : accordingly. what's the end result of setting these vs not? -- To view, visit https://review.coreboot.org/c/coreboot/+/85691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247 Gerrit-Change-Number: 85691 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 21:51:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Use the new Intel Bluetooth driver
by Matt DeVillier (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Alicja Michalska, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84636?usp=email ) Change subject: mb/starlabs/*: Use the new Intel Bluetooth driver ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6438a21a73e8ddab21fb5b9021fb4d5e2f8c1c22 Gerrit-Change-Number: 84636 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 21:50:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add core scaling factors read support
by Bora Guvendik (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85554?usp=email ) Change subject: soc/intel/pantherlake: Add core scaling factors read support ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Gerrit-Change-Number: 85554 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 21:16:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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