coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Hide peg11 to squelch warning
by Keith Hui (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Elyes Haouas, Keith Hui. Hello Elyes Haouas, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82633?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Elyes Haouas, Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-m: Hide peg11 to squelch warning ...................................................................... mb/asus/p8z77-m: Hide peg11 to squelch warning All 16 IVB PCIe lanes go to one x16 slot without bifurcation. There is no use for peg11. Hide it to squelch the leftover devices warning. Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82633/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8 Gerrit-Change-Number: 82633 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/starlabs/*: Correct the configuration for WLAN Wake
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86184?usp=email ) Change subject: mb/starlabs/*: Correct the configuration for WLAN Wake ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12797875acacc231e155ab4e427a950a3b1b9703 Gerrit-Change-Number: 86184 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:55:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: tree: Use true, false for dptf_enable
by Erik van den Bogaert (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Eric Lai, Frans Hendriks, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Maxim Polyakov, Michał Żygowski, Nick Vaccaro, Piotr Król, Subrata Banik, Tarun. Erik van den Bogaert has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86183?usp=email ) Change subject: tree: Use true, false for dptf_enable ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8 Gerrit-Change-Number: 86183 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:50:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: tree: Use true, false for dptf_enable
by Elyes Haouas (Code Review) 28 Jan '25

28 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86183?usp=email ) Change subject: tree: Use true, false for dptf_enable ...................................................................... tree: Use true, false for dptf_enable dptf_enable is a boolean, so use true false instead of 0 1. Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/aoostar/wtr_r1/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/brya/variants/uldrenite/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 53 files changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86183/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 9151d7f..1338292 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -27,7 +27,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index a802cca..18109c8 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -12,7 +12,7 @@ register "sagv" = "SaGv_Enabled" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "s0ix_enable" = "true" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 59e297c..d999973 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -15,7 +15,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "PrimaryDisplay" = "Display_PEG" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 4c7aa16..d7070fe 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -22,7 +22,7 @@ register "eist_enable" = "true" # DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f0370ed..8904516 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -25,7 +25,7 @@ register "disable_c1_state_auto_demotion" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 18f02e6..3009f65 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -18,7 +18,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b7b22d9..6160ebf 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,7 +19,7 @@ register "disable_package_c_state_demotion" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 481bd2e..6bd659d 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -15,7 +15,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 30e8309..65d3518 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -32,7 +32,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 5dae5f3..4e21cde 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -23,7 +23,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 5374666..cdc777b 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -23,7 +23,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index f7ff776..d792bc9 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -5,7 +5,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "5" # TCC of 100 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d..2b55e7c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ register "DdiPortCDdc" = "1" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Power limit config register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 561685f..971d886 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 25, .tdp_pl2_override = 51, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 5c9ce5d..9c1cc44 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -184,7 +184,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 1eda1ab..ed83f86 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4d3d517..7ae5255 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8c33f02..0b4558b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 138499c..671150d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ register "lpss_s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 0e1d210..5f81bec 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 5180bd9..51ba199 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 4a69cb3..c93cc4b 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index f6116eff..1187636 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 1573238..289cc72 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -21,7 +21,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 5a12bdc..7869dc5 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 1274b78..f9edf26 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 08880cb..2eee315 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 8b42a1c..5eee33e 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 0c1f122..ecfd522 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 41e6669..5385aaa 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index abab168..f27d26a 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -43,7 +43,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 81cbef5..e755776 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 19eb34e..901d408 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -45,7 +45,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 2523fb9..b973cef 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 04b7cf6..1048acb 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -45,7 +45,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 4aba20b..6df6c73 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 7eec7a8..d245844 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,7 +28,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e01e660..569abe5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,7 +31,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index aa5c08f..ac55ac0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,7 +198,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable External Bypass register "external_bypass" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 74ceca1..031b2f0 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -133,7 +133,7 @@ register "tcss_aux_ori" = "0" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index c3b398d..1eff945 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -17,7 +17,7 @@ register "sagv" = "SaGv_Enabled" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # eMMC HS400 register "emmc_enable_hs400_mode" = "true" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 7a46e10..dc0ae8a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "emmc_tx_cmd_cntl" = "0x1305" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override: 7.5W setting gives a run-time 6W actual # Set RAPL PL2 to 15W. diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 4bcdddd..56c7bd6 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -116,7 +116,7 @@ }" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index dc44770..473e586 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "IoBufferOwnership" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index e5480e2..1a565e5 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index d4f2ea3..6d14b58 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -115,7 +115,7 @@ register "pch_hda_idisp_codec_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device ref igpu on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 69ec546..70adca6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -71,7 +71,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fbb8418..d1deea3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -78,7 +78,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 953c819..3291e1d 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -3,7 +3,7 @@ chip soc/intel/apollolake register "enable_vtd" = "1" - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f129128..3b440a0b 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -24,7 +24,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d2d55de..fd20b15 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -15,7 +15,7 @@ register "eist_enable" = "true" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" register "tcc_offset" = "5" # TCC of 95C diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 610c737..18ffb1b 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -35,7 +35,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 426a289..13ca6e7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -16,7 +16,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/86183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8 Gerrit-Change-Number: 86183 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[XS] Change in coreboot[main]: soc/intel/common/pmc: Change GPE DW duplicate message to warning
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Subrata Banik. Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86174?usp=email ) Change subject: soc/intel/common/pmc: Change GPE DW duplicate message to warning ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Gerrit-Change-Number: 86174 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:18:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:16:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/amd/birman_plus: Fix flash size
by Patrick Rudolph (Code Review) 28 Jan '25

28 Jan '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86179?usp=email ) Change subject: mb/amd/birman_plus: Fix flash size ...................................................................... mb/amd/birman_plus: Fix flash size Birman+ has a 64MiB flash chip. Update the mainboards Kconfig comment and fix the FMD to generate a 64MiB ROM. Until now only the first 16MiB are being used. TEST: Still boots on AMD/Birman+ Change-Id: I72e3dcb0c3a308c3b0fd981b56cc7c1ef60095cc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/board_glinda.fmd 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/86179/1 diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 462fece..2e5b1a9 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -2,7 +2,7 @@ config BOARD_AMD_BIRMANPLUS_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM + select BOARD_ROMSIZE_KB_16384 # Birman+ actually has a 64MiB ROM select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd index 25c5113..bbb2239 100644 --- a/src/mainboard/amd/birman_plus/board_glinda.fmd +++ b/src/mainboard/amd/birman_plus/board_glinda.fmd @@ -1,5 +1,5 @@ -FLASH@0xFF000000 16M { - BIOS { +FLASH 64M { + BIOS 16M { EC_SIG 4K FMAP 4K COREBOOT(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/86179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72e3dcb0c3a308c3b0fd981b56cc7c1ef60095cc Gerrit-Change-Number: 86179 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: mb/amd/birman_plus: Add SMMSTORE to FMAP
by Patrick Rudolph (Code Review) 28 Jan '25

28 Jan '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86177?usp=email ) Change subject: mb/amd/birman_plus: Add SMMSTORE to FMAP ...................................................................... mb/amd/birman_plus: Add SMMSTORE to FMAP Add the SMMSTORE region to the default FMAP to allow building for EDK2 as payload. TEST: Still boots on AMD/Birman+ Change-Id: I661fcc55bf30aa6f1f3cc8a57e6d0eaf2fed4621 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/amd/birman_plus/board_glinda.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/86177/1 diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd index 7567090..25c5113 100644 --- a/src/mainboard/amd/birman_plus/board_glinda.fmd +++ b/src/mainboard/amd/birman_plus/board_glinda.fmd @@ -3,6 +3,7 @@ EC_SIG 4K FMAP 4K COREBOOT(CBFS) + SMMSTORE(PRESERVE)@15616K 256K EC_BODY@15872K 256K RW_MRC_CACHE 120K } -- To view, visit https://review.coreboot.org/c/coreboot/+/86177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I661fcc55bf30aa6f1f3cc8a57e6d0eaf2fed4621 Gerrit-Change-Number: 86177 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/common/pmc: Fix duplicate GPE DW register check
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Subrata Banik. Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86173?usp=email ) Change subject: soc/intel/common/pmc: Fix duplicate GPE DW register check ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591 Gerrit-Change-Number: 86173 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:12:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Fallback to the GNA being disabled
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86176?usp=email ) Change subject: mb/starlabs/starbook/mtl: Fallback to the GNA being disabled ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7779781266a63c8c9f779d25ff2c692bb498c594 Gerrit-Change-Number: 86176 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 28 Jan 2025 13:11:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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