coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/starlabs/starbook: Only show Hyper-Threading option when relevant
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86166?usp=email ) Change subject: mb/starlabs/starbook: Only show Hyper-Threading option when relevant ...................................................................... mb/starlabs/starbook: Only show Hyper-Threading option when relevant Guard the Hyper-Threading option against SOC_INTEL_ALDERLAKE_PCH_N, as the N200 processors used don't support it. Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86166 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/cfr.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c index 9efe924..7316f2a 100644 --- a/src/mainboard/starlabs/starbook/cfr.c +++ b/src/mainboard/starlabs/starbook/cfr.c @@ -97,12 +97,14 @@ }); #endif +#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) static const struct sm_object hyper_threading = SM_DECLARE_BOOL({ .opt_name = "hyper_threading", .ui_name = "Hyper-Threading", .ui_helptext = "Enable or disable Hyper-Threading", .default_value = true, }); +#endif static const struct sm_object kbl_timeout = SM_DECLARE_ENUM({ .opt_name = "kbl_timeout", @@ -291,7 +293,9 @@ .obj_list = (const struct sm_object *[]) { &me_state, &me_state_counter, + #if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) &hyper_threading, + #endif &vtd, NULL }, -- To view, visit https://review.coreboot.org/c/coreboot/+/86166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929 Gerrit-Change-Number: 86166 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun, Werner Zeh. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86164/comment/78c277d7_f236760d?us… : PS5, Line 11: This prevented platforms from : disabling GPE routing via PMC by setting all DW values to zero. > no, it prevented platforms from using the default GPE routing by not programming the routes in devic […] Acknowledged File src/soc/intel/alderlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/86164/comment/7147b69d_213917b0?us… : PS3, Line 164: override > > > do we really need this here? there's already another printk in this case (PMC: Using default GPE […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 09:17:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/common/pmc: Change GPE DW duplicate message to warning
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86174?usp=email ) Change subject: soc/intel/common/pmc: Change GPE DW duplicate message to warning ...................................................................... soc/intel/common/pmc: Change GPE DW duplicate message to warning The message printed when duplicate GPE DW register values are detected was previously logged at the INFO level. This commit changes the log level to WARNING, as duplicate DW values indicate a potential misconfiguration and warrant closer attention. While the system falls back to the default GPE route (as per MISCCFG register), this situation should be investigated to ensure correct platform configuration. This change ensures that developers are more clearly notified of potential GPE routing issues. TEST=Built and booted on a platform using PMC GPE routing. Verified that the message is printed at the WARNING level when duplicate DW values are present. Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/86174/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 18a527a..a049cf2 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -657,7 +657,8 @@ * are different, and if they aren't use the reset values. */ if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + printk(BIOS_WARNING, "PMC: Duplicate GPE DWx register value detected hence " + "using default GPE route from MISCCFG register\n"); gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG); dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; -- To view, visit https://review.coreboot.org/c/coreboot/+/86174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Gerrit-Change-Number: 86174 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/common/pmc: Fix duplicate GPE DW register check
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86173?usp=email ) Change subject: soc/intel/common/pmc: Fix duplicate GPE DW register check ...................................................................... soc/intel/common/pmc: Fix duplicate GPE DW register check The `pmc_gpe_init` function's check for duplicate GPE DW register values was incomplete. It only checked for duplicates between DW0 and DW1, and DW1 and DW2, but failed to check if DW0 and DW2 were the same. This could lead to incorrect GPE routing if DW0 and DW2 happened to have the same value, even if DW1 was different. This commit corrects the check to ensure that all three DW registers (DW0, DW1, and DW2) are compared against each other. If any two registers have the same value, a message is printed indicating that the default GPE route will be used. Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86173/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0fadd6e..18a527a 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -656,7 +656,7 @@ * Route the GPIOs to the GPE0 block. Determine that all values * are different, and if they aren't use the reset values. */ - if (dw0 == dw1 || dw1 == dw2) { + if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) { printk(BIOS_INFO, "PMC: Using default GPE route.\n"); gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG); -- To view, visit https://review.coreboot.org/c/coreboot/+/86173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591 Gerrit-Change-Number: 86173 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Hello Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86164?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers ...................................................................... soc/intel: Allow zero values for PMC GPE0 DW registers The `pmc_gpe0_different_values` function previously asserted if any two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as introduced in commit 640a41f3ee938b794b14 ("soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique"). This prevented platforms from configuring GPE routing via PMC as per default register (MISCCFG) value. This commit modifies the check to allow all DW registers to be zero. This enables platforms that relies on MISCCFG register for PMC-controlled GPE routing to boot without triggering the assertion. The change was verified by testing the following scenarios: - All DWs zero: The system boots using the default GPE route. No assertion occurs. - Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion is triggered as expected. - Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur. TEST=Built and booted normally. No assertion failure observed. Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 9 files changed, 63 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86164/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Paul Menzel. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86143?usp=email ) Change subject: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86143/comment/4e0767a8_915d4f55?us… : PS1, Line 9: FP > Spell it out in the beginning? Acknowledged https://review.coreboot.org/c/coreboot/+/86143/comment/8810111b_6e6b002f?us… : PS1, Line 10: hardware design > Append schematic names. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Gerrit-Change-Number: 86143 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 09:13:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Subrata Banik. Hello Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86143?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0 ...................................................................... mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0 This moves the FPS device from GSPI0A to GSPI0 to align with the hardware design dated Jan'25. The FPS device was initially placed on GSPI0A, which was incorrect. This commit rectifies the configuration by moving it to the correct GSPI0 interface. This change ensures that the CRFP device is correctly connected and functions as expected. BUG=b:377595986 TEST=Able to build and boot google/fatcat. Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86143/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Gerrit-Change-Number: 86143 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Move FP from GSPI0A to GSPI0
by Paul Menzel (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Subrata Banik. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86143?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat: Move FP from GSPI0A to GSPI0 ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Patchset: PS1: Feel free to ignore and mark as resolved. Commit Message: https://review.coreboot.org/c/coreboot/+/86143/comment/87ef7deb_79cb44e2?us… : PS1, Line 9: FP Spell it out in the beginning? https://review.coreboot.org/c/coreboot/+/86143/comment/6f60f44b_6362b625?us… : PS1, Line 10: hardware design Append schematic names. -- To view, visit https://review.coreboot.org/c/coreboot/+/86143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Gerrit-Change-Number: 86143 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 09:10:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/mrc_cache: Measure MRC cache as runtime data
by Paul Menzel (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Arthur Heymans, Christian Walter, Ivan Kuzneczov, Julius Werner. Paul Menzel has posted comments on this change by Ivan Kuzneczov. ( https://review.coreboot.org/c/coreboot/+/85605?usp=email ) Change subject: drivers/mrc_cache: Measure MRC cache as runtime data ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85605/comment/f2ab34b4_4d2a83b3?us… : PS5, Line 10: restore Which commit changed it? https://review.coreboot.org/c/coreboot/+/85605/comment/5db0381c_ed8a9e58?us… : PS5, Line 16: https://badram.eu/ )will Space after ). File src/security/tpm/Kconfig: https://review.coreboot.org/c/coreboot/+/85605/comment/1c8b5787_2270889d?us… : PS5, Line 87: Measures MRC cache as runtime data Maybe elaborate for users, why this is useful? -- To view, visit https://review.coreboot.org/c/coreboot/+/85605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d82642c24de1b317851d0afd44985195e92c104 Gerrit-Change-Number: 85605 Gerrit-PatchSet: 5 Gerrit-Owner: Ivan Kuzneczov <ivan.kuzneczov(a)hardenedvault.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ivan Kuzneczov <ivan.kuzneczov(a)hardenedvault.net> Gerrit-Comment-Date: Tue, 28 Jan 2025 08:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: fatcat-ish: disable UART0 RX
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N. Subrata Banik has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email ) Change subject: fatcat-ish: disable UART0 RX ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/86005/comment/45a81031_aeebc5f5?us… : PS2, Line 421: /* GPP_D05: NC */ : PAD_NC(GPP_D05, NONE) > I updated problem statement, it happens when ISH switches is OFF, might be FPS is ON, or both are OFF. So inside FPS doesn't cover all cases. Ack https://review.coreboot.org/c/coreboot/+/86005/comment/0eef90aa_10372809?us… : PS2, Line 432: /* GPP_D05: ISH_UART0_RXD */ : PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), > We still have ISH log, just console doesn't accept input. With ISH PM enabled, anyway console doesn't pick up input most of the time because it's in LPM; not much impact from what I experienced. Can you please mention the same in the commit msg as well to ensure we know thar ISH console won't be able to receive a response w/ this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 3 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 08:58:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Li1 Feng <li1.feng(a)intel.com>

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coreboot-gerrit January 2025