coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/hp/pro_3x00_series: Remove unused ACPI brightness control
by Václav Straka (Code Review) 05 Jan '25

05 Jan '25

Václav Straka has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85847?usp=email ) Change subject: mb/hp/pro_3x00_series: Remove unused ACPI brightness control ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85847/comment/47e885a4_e7ad765e?us… : PS1, Line 7: Remove unused brightness control > Maybe: "Remove unused ACPI brightness control" to make it more clear what this patch is actually cha […] Done https://review.coreboot.org/c/coreboot/+/85847/comment/7556cee7_af8701b1?us… : PS1, Line 10: a display > Maybe: "an integrated display" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85847?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2 Gerrit-Change-Number: 85847 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Jan 2025 00:01:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: mb/hp/pro_3x00_series: Remove unused ACPI brightness control
by Václav Straka (Code Review) 05 Jan '25

05 Jan '25

Attention is currently required from: Václav Straka. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85847?usp=email to look at the new patch set (#2). Change subject: mb/hp/pro_3x00_series: Remove unused ACPI brightness control ...................................................................... mb/hp/pro_3x00_series: Remove unused ACPI brightness control These lines are not needed because this mainboard does not have an integrated display to control. Tested on HP Pro 3400 Series. Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2 Signed-off-by: Vesek <venda.straka(a)gmail.com> --- M src/mainboard/hp/pro_3x00_series/dsdt.asl 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85847/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85847?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2 Gerrit-Change-Number: 85847 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com>

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[L] Change in coreboot[main]: mb/samsung: Add Samsung Series 9 NP900X3D
by Name of user not set (Code Review) 04 Jan '25

04 Jan '25

Name of user not set #1005688 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85853?usp=email ) Change subject: mb/samsung: Add Samsung Series 9 NP900X3D ...................................................................... mb/samsung: Add Samsung Series 9 NP900X3D So far this is just the result of autoport with some lines edited. Upon booting, the only sign of life are the spinning fans and glowing power button. Signed-off-by: libreandre <openrc(a)posteo.de> Change-Id: Ic218c8ebfe4e98d2d18bb76d81a3b47232fb95fd --- A src/mainboard/samsung/900x3d/Kconfig A src/mainboard/samsung/900x3d/Kconfig.name A src/mainboard/samsung/900x3d/Makefile.mk A src/mainboard/samsung/900x3d/acpi/ec.asl A src/mainboard/samsung/900x3d/acpi/platform.asl A src/mainboard/samsung/900x3d/acpi/superio.asl A src/mainboard/samsung/900x3d/acpi_tables.c A src/mainboard/samsung/900x3d/board_info.txt A src/mainboard/samsung/900x3d/devicetree.cb A src/mainboard/samsung/900x3d/dsdt.asl A src/mainboard/samsung/900x3d/early_init.c A src/mainboard/samsung/900x3d/gma-mainboard.ads A src/mainboard/samsung/900x3d/gpio.c A src/mainboard/samsung/900x3d/hda_verb.c A src/mainboard/samsung/900x3d/mainboard.c 15 files changed, 616 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85853/1 diff --git a/src/mainboard/samsung/900x3d/Kconfig b/src/mainboard/samsung/900x3d/Kconfig new file mode 100644 index 0000000..4278d41 --- /dev/null +++ b/src/mainboard/samsung/900x3d/Kconfig @@ -0,0 +1,38 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SAMSUNG_ELECTRONICS_CO_LTD_900X3D + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "samsung/900x3d" + +config MAINBOARD_PART_NUMBER + string + default "900X3D" + +config VGA_BIOS_ID + string + default "8086,0116" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/samsung/900x3d/Kconfig.name b/src/mainboard/samsung/900x3d/Kconfig.name new file mode 100644 index 0000000..2a0bd8e --- /dev/null +++ b/src/mainboard/samsung/900x3d/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SAMSUNG_ELECTRONICS_CO_LTD_900X3D + bool "900X3D" diff --git a/src/mainboard/samsung/900x3d/Makefile.mk b/src/mainboard/samsung/900x3d/Makefile.mk new file mode 100644 index 0000000..fb492d3 --- /dev/null +++ b/src/mainboard/samsung/900x3d/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/samsung/900x3d/acpi/ec.asl b/src/mainboard/samsung/900x3d/acpi/ec.asl new file mode 100644 index 0000000..7ee0e29 --- /dev/null +++ b/src/mainboard/samsung/900x3d/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/900x3d/acpi/platform.asl b/src/mainboard/samsung/900x3d/acpi/platform.asl new file mode 100644 index 0000000..2d24bbd --- /dev/null +++ b/src/mainboard/samsung/900x3d/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/900x3d/acpi/superio.asl b/src/mainboard/samsung/900x3d/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/samsung/900x3d/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/samsung/900x3d/acpi_tables.c b/src/mainboard/samsung/900x3d/acpi_tables.c new file mode 100644 index 0000000..e275965 --- /dev/null +++ b/src/mainboard/samsung/900x3d/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/samsung/900x3d/board_info.txt b/src/mainboard/samsung/900x3d/board_info.txt new file mode 100644 index 0000000..a07c49b --- /dev/null +++ b/src/mainboard/samsung/900x3d/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +Release year: 2012 +FIXME: put ROM package, ROM socketed diff --git a/src/mainboard/samsung/900x3d/devicetree.cb b/src/mainboard/samsung/900x3d/devicetree.cb new file mode 100644 index 0000000..98fdaa7 --- /dev/null +++ b/src/mainboard/samsung/900x3d/devicetree.cb @@ -0,0 +1,108 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000e57" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12281228" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here" + device domain 0x0 on + device ref host_bridge on # Host bridge Host bridge + subsystemid 0x144d 0xc0d3 + end + device ref peg10 off # PEG + end + device ref igd on # iGPU + subsystemid 0x144d 0xc0d3 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x0000162c" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x000c0a01" + register "gen4_dec" = "0x000c06a1" + register "gpi7_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {0, 1, 0}, + {1, 1, 0}, + {1, 1, 1}, + {0, 1, 1}, + {1, 0, 2}, + {1, 0, 2}, + {0, 0x153, 3}, + {0, 0x153, 3}, + {0, 0xf57, 4}, + {0, 0xf57, 4}, + {0, 0x153, 5}, + {0, 0x153, 5}, + {0, 0x153, 6}, + {0, 0x153, 6}, + }" + device ref mei1 on # Management Engine Interface 1 + subsystemid 0x144d 0xc0d3 + end + device ref mei2 off # Management Engine Interface 2 + end + device ref me_ide_r off # Management Engine IDE-R + end + device ref me_kt off # Management Engine KT + end + device ref gbe off # Intel Gigabit Ethernet + end + device ref ehci2 off # USB2 EHCI #2 + end + device ref hda on # High Definition Audio + subsystemid 0x144d 0xc0d3 + end + device ref pcie_rp1 on # PCIe Port #1 + subsystemid 0x144d 0xc0d3 + end + device ref pcie_rp2 off # PCIe Port #2 + end + device ref pcie_rp3 off # PCIe Port #3 + end + device ref pcie_rp4 on # PCIe Port #4 + subsystemid 0x144d 0xc0d3 + end + device ref pcie_rp5 on # PCIe Port #5 + subsystemid 0x144d 0xc0d3 + end + device ref pcie_rp6 off # PCIe Port #6 + end + device ref pcie_rp7 off # PCIe Port #7 + end + device ref pcie_rp8 off # PCIe Port #8 + end + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x144d 0xc0d3 + end + device ref pci_bridge off # PCI bridge + end + device ref lpc on # LPC bridge + subsystemid 0x144d 0xc0d3 + end + device ref sata1 on # SATA Controller 1 + subsystemid 0x144d 0xc0d3 + end + device ref smbus on # SMBus + subsystemid 0x144d 0xc0d3 + end + device ref sata2 off # SATA Controller 2 + end + device ref thermal off # Thermal + end + end + end +end diff --git a/src/mainboard/samsung/900x3d/dsdt.asl b/src/mainboard/samsung/900x3d/dsdt.asl new file mode 100644 index 0000000..cee4939 --- /dev/null +++ b/src/mainboard/samsung/900x3d/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/samsung/900x3d/early_init.c b/src/mainboard/samsung/900x3d/early_init.c new file mode 100644 index 0000000..ae74247 --- /dev/null +++ b/src/mainboard/samsung/900x3d/early_init.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} diff --git a/src/mainboard/samsung/900x3d/gma-mainboard.ads b/src/mainboard/samsung/900x3d/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/samsung/900x3d/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/samsung/900x3d/gpio.c b/src/mainboard/samsung/900x3d/gpio.c new file mode 100644 index 0000000..71732d4 --- /dev/null +++ b/src/mainboard/samsung/900x3d/gpio.c @@ -0,0 +1,265 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/samsung/900x3d/hda_verb.c b/src/mainboard/samsung/900x3d/hda_verb.c new file mode 100644 index 0000000..cf7326d --- /dev/null +++ b/src/mainboard/samsung/900x3d/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x144dc0d3, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x144dc0d3), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11840), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/samsung/900x3d/mainboard.c b/src/mainboard/samsung/900x3d/mainboard.c new file mode 100644 index 0000000..bec7c59 --- /dev/null +++ b/src/mainboard/samsung/900x3d/mainboard.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x80, 0x00, 0x03, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x01, 0x31, 0x0a, 0xb8, 0x05, 0x38, 0x1d, 0x3a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* b0 */ 0x16, 0xf8, 0x15, 0xe0, 0x1d, 0x9c, 0x00, 0xa8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* c0 */ 0x31, 0x00, 0x29, 0x26, 0x00, 0xff, 0x00, 0x01, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x4a, + /* d0 */ 0x00, 0x66, 0x00, 0xc0, 0x05, 0x38, 0x0b, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* e0 */ 0x34, 0x32, 0x30, 0x34, 0x4c, 0x35, 0x38, 0x00, 0x4c, 0x69, 0x50, 0x00, 0xff, 0xff, 0xff, 0xff, + /* f0 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic218c8ebfe4e98d2d18bb76d81a3b47232fb95fd Gerrit-Change-Number: 85853 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1005688

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[XS] Change in coreboot[main]: mb/emulation/spike-riscv/uart.c: Update UART address
by Maximilian Brune (Code Review) 04 Jan '25

04 Jan '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85852?usp=email ) Change subject: mb/emulation/spike-riscv/uart.c: Update UART address ...................................................................... mb/emulation/spike-riscv/uart.c: Update UART address Spike Simualator commit 191634d2854d implemented a ns16550 serial device which puts the base address at 0x10000000. Tested: Start Spike Simulator and see that coreboot prints onto the UART. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83 --- M src/mainboard/emulation/spike-riscv/uart.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/85852/1 diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 4ea2466..e93594c 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -5,5 +5,5 @@ uintptr_t uart_platform_base(unsigned int idx) { - return (uintptr_t)0x02100000; + return (uintptr_t)0x10000000; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83 Gerrit-Change-Number: 85852 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Nicholas Chin (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email ) Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 21:20:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Riku Viitanen (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email ) Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... Patch Set 11: (2 comments) File src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85832/comment/e737b7d4_476b6723?us… : PS10, Line 34: device ref mei1 on end > Oh, I guess with the subsystemid entries removed this is now unnecessary as it's the same as the chi […] Hmm, same with host_bridge, ehci1, ehci2 https://review.coreboot.org/c/coreboot/+/85832/comment/37727e4b_27172690?us… : PS10, Line 99: device ref smbus on end > Same here, can be removed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 20:53:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Riku Viitanen (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85832?usp=email to look at the new patch set (#11). Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... mb/asus/h61-series: Add P8H67-I DELUXE variant On vendor firmware, the IFD is read-only and ME completely locked. But the BIOS region can be internally flashed with coreboot. Super I/O GP15 is connected to HDA_SDO, potentially enabling write access to entire flash. Simply setting this GPIO, and restarting the board wasn't enough. Tested: - i5-2500K - 8GB or 2x8GB Hynix HMT41GS6BFR8A-RD (@1333MHz) - 8+4GB Hynix HMT351S6EFR8A-PB (@1333MHz) - Internal SATA ports - Realtek Ethernet - libgfxinit, onboard DVI - All rear USB and USB3 ports, internal Bluetooth dongle is detected - SeaBIOS boots to Void Linux and Devuan - PS/2 keyboard and mouse (only combo port, one at a time) - PEG slot - Mini-PCIe WLAN slot Not tested: - eSATA - SPDIF - LEDs: front panel Not working: - Super I/O shows weird temperatures in lm_sensors: CPU -51°C AUX +84°C - Resuming from S3 when root partition is on an USB 3.0 stick (works when it's attached to USB 2.0 or SATA). - DRAM_LED (on vendor firmware, it stays lit if there are DRAM problems) Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/h61-series/Kconfig.name A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb 11 files changed, 443 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85832/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Nicholas Chin (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email ) Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... Patch Set 10: (2 comments) File src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85832/comment/4c971455_f5d8c8c1?us… : PS10, Line 34: device ref mei1 on end Oh, I guess with the subsystemid entries removed this is now unnecessary as it's the same as the chipset devicetree. https://review.coreboot.org/c/coreboot/+/85832/comment/206c7f99_43371379?us… : PS10, Line 99: device ref smbus on end Same here, can be removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 10 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 20:43:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Riku Viitanen (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85832?usp=email to look at the new patch set (#10). Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... mb/asus/h61-series: Add P8H67-I DELUXE variant On vendor firmware, the IFD is read-only and ME completely locked. But the BIOS region can be internally flashed with coreboot. Super I/O GP15 is connected to HDA_SDO, potentially enabling write access to entire flash. Simply setting this GPIO, and restarting the board wasn't enough. Tested: - i5-2500K - 8GB or 2x8GB Hynix HMT41GS6BFR8A-RD (@1333MHz) - 8+4GB Hynix HMT351S6EFR8A-PB (@1333MHz) - Internal SATA ports - Realtek Ethernet - libgfxinit, onboard DVI - All rear USB and USB3 ports, internal Bluetooth dongle is detected - SeaBIOS boots to Void Linux and Devuan - PS/2 keyboard and mouse (only combo port, one at a time) - PEG slot - Mini-PCIe WLAN slot Not tested: - eSATA - SPDIF - LEDs: front panel Not working: - Super I/O shows weird temperatures in lm_sensors: CPU -51°C AUX +84°C - Resuming from S3 when root partition is on an USB 3.0 stick (works when it's attached to USB 2.0 or SATA). - DRAM_LED (on vendor firmware, it stays lit if there are DRAM problems) Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/h61-series/Kconfig.name A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/board_info.txt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.default A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/cmos.layout A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/data.vbt A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gma-mainboard.ads A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/gpio.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/hda_verb.c A src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb 11 files changed, 448 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85832/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 10 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/asus/h61-series: Add P8H67-I DELUXE variant
by Riku Viitanen (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85832?usp=email ) Change subject: mb/asus/h61-series: Add P8H67-I DELUXE variant ...................................................................... Patch Set 8: (6 comments) File src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/early_init.c: https://review.coreboot.org/c/coreboot/+/85832/comment/4439c7f3_884f51db?us… : PS7, Line 8: PCI_DEV(0, 0x1f, 0), 0x82, 0x3f00 > Could be replaced with macros in `sb/intel/bd82x6x/pch.h`: […] Done https://review.coreboot.org/c/coreboot/+/85832/comment/866e7018_1e7127af?us… : PS7, Line 9: PCI_DEV(0, 0x1f, 0), 0x80, 0x0010 > Same here: […] removed File src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb: PS7: > Add SPDX header Done https://review.coreboot.org/c/coreboot/+/85832/comment/8e4a889a_615c65d2?us… : PS7, Line 2: register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4" > Move under igd Done https://review.coreboot.org/c/coreboot/+/85832/comment/d5871938_b80402c1?us… : PS7, Line 40: subsystemid 0x1043 0x848d > It looks like it is possible to use a `subsystemid 0xnnnn 0xnnnn inherit` and then still specify a s […] Done https://review.coreboot.org/c/coreboot/+/85832/comment/18576708_be78afe1?us… : PS7, Line 62: device ref pci_bridge off end > Defaults to off in chipset devicetree and can be removed from the overridetree Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703 Gerrit-Change-Number: 85832 Gerrit-PatchSet: 8 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 19:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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coreboot-gerrit January 2025