coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: util/chromeos/crosfirmware: Add special handling for REEF board
by Felix Singer (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/85873?usp=email ) Change subject: util/chromeos/crosfirmware: Add special handling for REEF board ...................................................................... Patch Set 1: Code-Review+2 (2 comments) File util/chromeos/crosfirmware.sh: https://review.coreboot.org/c/coreboot/+/85873/comment/c0aa50af_e4714795?us… : PS1, Line 109: | I would have assumed that a line continuation (`\`) is needed at the end, but other lines don't have one as well. https://review.coreboot.org/c/coreboot/+/85873/comment/dc74ab22_2cc581fb?us… : PS1, Line 110: \ While on it, maybe put it in between single quotation marks? -- To view, visit https://review.coreboot.org/c/coreboot/+/85873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588 Gerrit-Change-Number: 85873 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 01:32:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85861?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/dp/dptx_hal_common.c: https://review.coreboot.org/c/coreboot/+/85861/comment/5d7977e5_be50d977?us… : PS3, Line 115: DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); > This would be wrong for mt8196, where its code is `mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val […] I define `DP_CLRSETBITS` on mt8196 like this. ``` #define DP_CLRSETBITS(mtk_dp, reg, var, mask) \ mtk_dp_mask(mtk_dp, (reg) - (reg) % 2, \ (var) << (8 * ((reg) % 2)), (mask) << (8 * ((reg) % 2))) ``` `mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val << 8, 0x7 << 8)` is converted to `DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7)`. -- To view, visit https://review.coreboot.org/c/coreboot/+/85861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Gerrit-Change-Number: 85861 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 01:31:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/dp/dptx_common.c: https://review.coreboot.org/c/coreboot/+/85860/comment/68f0eb51_853172c0?us… : PS4, Line 281: union misc_t dptx_misc; > Not related to this patch, but some fields are not initialized. We should write `dptx_misc = { . […] Do you suggest fixing it in a separate patch or in the same patch ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 01:22:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... Patch Set 2: (17 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85842/comment/72696bda_a32e63b4?us… : PS1, Line 9: Mt8196 > MT8196 Done https://review.coreboot.org/c/coreboot/+/85842/comment/e3dbfd83_3ea81fe1?us… : PS1, Line 8: : Mt8196 use new RC mode with clk_buf driver, and need srclken_rc to send : cmd. > Can you elaborate more ? What is RC mode ? What is this driver for ? Done Commit Message: https://review.coreboot.org/c/coreboot/+/85842/comment/3a69a782_245958e4?us… : PS2, Line 9: need needs https://review.coreboot.org/c/coreboot/+/85842/comment/e805b473_e0829b53?us… : PS2, Line 9: use uses https://review.coreboot.org/c/coreboot/+/85842/comment/7d85315e_465177dd?us… : PS2, Line 10: , remove https://review.coreboot.org/c/coreboot/+/85842/comment/37af66a6_86b00513?us… : PS2, Line 11: , and so on remove File src/soc/mediatek/mt8196/include/soc/srclken_rc.h: https://review.coreboot.org/c/coreboot/+/85842/comment/2357ed62_9d4f469e?us… : PS1, Line 192: > remove one tab Done https://review.coreboot.org/c/coreboot/+/85842/comment/0d3e8481_88b18fce?us… : PS1, Line 202: > Remove 2 tabs Done File src/soc/mediatek/mt8196/srclken_rc.c: https://review.coreboot.org/c/coreboot/+/85842/comment/a490502b_db541195?us… : PS1, Line 69: #define SW_BBLPM_HIGH 1 : #define SW_BBLPM_LOW 0 : #define SW_FPM_HIGH 1 : #define SW_FPM_LOW 0 > use enum ? Done https://review.coreboot.org/c/coreboot/+/85842/comment/fe997c5e_e0ffc1a9?us… : PS1, Line 149: | > move `|` to above line Done https://review.coreboot.org/c/coreboot/+/85842/comment/86b32352_486e34a0?us… : PS1, Line 278: DCXO_SETTLE_BLK_EN > align with first param Done https://review.coreboot.org/c/coreboot/+/85842/comment/c13dcb73_76ff75d3?us… : PS1, Line 318: id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); > move to above line Done https://review.coreboot.org/c/coreboot/+/85842/comment/fb6aa213_e78d0bd1?us… : PS1, Line 320: > remove one blank line Done https://review.coreboot.org/c/coreboot/+/85842/comment/117e53dd_9ce99ae9?us… : PS1, Line 359: retry(ACK_DELAY_TIMES, (read32(&rc_status_regs->rc_mxx_req_sta_0[chn]) & 0xa) == state, udelay(ACK_DELAY_US)) > ``` […] Done https://review.coreboot.org/c/coreboot/+/85842/comment/87f493f6_9f6bbeb1?us… : PS1, Line 360: 0x%x > %#x Done https://review.coreboot.org/c/coreboot/+/85842/comment/76acfe36_d6ad0191?us… : PS1, Line 362: chn, > move to the above line Done https://review.coreboot.org/c/coreboot/+/85842/comment/9b14fb0b_80986355?us… : PS1, Line 385: dsb > I have the same question. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 00:09:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling pmif_spmi_enable_swinf
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Fix MT6363 buck5 enablement
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

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[L] Change in coreboot[main]: mb/asus: Add Maximus VI Hero (Haswell)
by Jan Philipp Groß (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85872?usp=email ) Change subject: mb/asus: Add Maximus VI Hero (Haswell) ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hey guys, this is the big brother of the the Gene (M-ATX). Ported to the best of my abilities. Best regards -- To view, visit https://review.coreboot.org/c/coreboot/+/85872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5efa914903170510848668b68d5847f75c9af0eb Gerrit-Change-Number: 85872 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 23:27:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC
by Jérémy Compostella (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85874?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC ...................................................................... mb/google/fatcat: Enable EC ACPI memmap for Microchip EC This commit enables ACPI memory mapping for fatcat boards featuring a Microchip Embedded Controller (EC). This allows the operating system to access and read various information from the EC. The Microchip EC does not directly map these registers to I/O space, necessitating the use of an indirection mechanism for register access. TEST=/sys/class/power_supply/BAT0/* reports consistent values Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85874/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba Gerrit-Change-Number: 85874 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC
by Jérémy Compostella (Code Review) 06 Jan '25

06 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85874?usp=email ) Change subject: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC ...................................................................... mb/google/fatcat: Enable EC ACPI memmap for Microchip EC This commit enables ACPI memory mapping for fatcat boards featuring a Microchip Embedded Controller (EC). This allows the operating system to access and read various information from the EC. The Microchip EC does not directly map these registers to I/O space, necessitating the use of an indirection mechanism for register access. TEST=/sys/class/power_supply/BAT0/* reports consistent values Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> q Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85874/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 37ba330..3061004 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -61,11 +61,13 @@ config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION config BOARD_GOOGLE_FATCATISH select BOARD_GOOGLE_MODEL_FATCAT + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION -- To view, visit https://review.coreboot.org/c/coreboot/+/85874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba Gerrit-Change-Number: 85874 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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coreboot-gerrit January 2025