coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel
by Yang Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85890?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel ...................................................................... mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel Add STA_2082109QFH040022_50E MIPI panel for wyrdeer. Datasheet: 2082109QFH040022-50E-XR109IB5T_Full viewing-300-51PIN- V1.0.pdf BUG=b:379810871 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I64b907da8ff4e88b9290132033b9300d0b9488cb --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/panel_wyrdeer.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/85890/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85890?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64b907da8ff4e88b9290132033b9300d0b9488cb Gerrit-Change-Number: 85890 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Kapil Porwal (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Nick Vaccaro, Rui Zhou. Kapil Porwal has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85850?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/rull/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85850/comment/b5a47fbc_c126e4e0?us… : PS2, Line 309: 4100 It is greater than 100% speed! -- To view, visit https://review.coreboot.org/c/coreboot/+/85850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Gerrit-Change-Number: 85850 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 08 Jan 2025 03:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel
by Yang Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85890?usp=email ) Change subject: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel ...................................................................... mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel Add STA_2082109QFH040022_50E MIPI panel for wyrdeer. Datasheet: 2082109QFH040022-50E-XR109IB5T_Full viewing-300-51PIN-V1.0.pdf BUG=b:379810871 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I64b907da8ff4e88b9290132033b9300d0b9488cb --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/panel_wyrdeer.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/85890/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 6977bd4..d8643fd 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -74,6 +74,7 @@ select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_KD_KD110N11_51IE if BOARD_GOOGLE_WYRDEER select MIPI_PANEL_LCE_LMFBX101117480 if BOARD_GOOGLE_WUGTRIO + select MIPI_PANEL_STA_2082109QFH040022_50E if BOARD_GOOGLE_WYRDEER select MIPI_PANEL_STA_ER88577 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE diff --git a/src/mainboard/google/corsola/panel_wyrdeer.c b/src/mainboard/google/corsola/panel_wyrdeer.c index 5ae3120..5d6379d 100644 --- a/src/mainboard/google/corsola/panel_wyrdeer.c +++ b/src/mainboard/google/corsola/panel_wyrdeer.c @@ -25,6 +25,14 @@ .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, + /* STA Technology panel */ + [9] = { + .configure_backlight = backlight_control, + .power_on = mipi_panel_power_on, + .name = "STA_2082109QFH040022_50E", + .disp_path = DISP_PATH_MIPI, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + }, }; struct panel_description *get_panel_description(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/85890?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64b907da8ff4e88b9290132033b9300d0b9488cb Gerrit-Change-Number: 85890 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: drivers/mipi: Add support for STA_2082109QFH040022_50E panel
by Yang Wu (Code Review) 08 Jan '25

08 Jan '25

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85889?usp=email ) Change subject: drivers/mipi: Add support for STA_2082109QFH040022_50E panel ...................................................................... drivers/mipi: Add support for STA_2082109QFH040022_50E panel Add STA panel STA_2082109QFH040022_50E serializable data to CBFS. Datasheet: 2082109QFH040022-50E-XR109IB5T_Full viewing-300-51PIN-V1.0.pdf BUG=b:379810871 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I131e179b7c4420e2038ec4023f9b2f505fc6c088 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/drivers/mipi/Kconfig M src/drivers/mipi/Makefile.mk A src/drivers/mipi/panel-STA_2082109QFH040022_50E.c 3 files changed, 133 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/85889/1 diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig index a7049ba..1edebf9 100644 --- a/src/drivers/mipi/Kconfig +++ b/src/drivers/mipi/Kconfig @@ -57,6 +57,9 @@ config MIPI_PANEL_STA_2081101QFH032011_53G bool +config MIPI_PANEL_STA_2082109QFH040022_50E + bool + config MIPI_PANEL_STA_ER88577 bool diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk index 0c4a5c9..de566d4 100644 --- a/src/drivers/mipi/Makefile.mk +++ b/src/drivers/mipi/Makefile.mk @@ -29,6 +29,7 @@ panel-params-$(CONFIG_MIPI_PANEL_LCE_LMFBX101117480) += panel-LCE_LMFBX101117480 panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G +panel-params-$(CONFIG_MIPI_PANEL_STA_2082109QFH040022_50E) += panel-STA_2082109QFH040022_50E panel-params-$(CONFIG_MIPI_PANEL_STA_ER88577) += panel-STA_ER88577 panel-params-$(CONFIG_MIPI_PANEL_STA_HIMAX83102_J02) += panel-STA_HIMAX83102_J02 panel-params-$(CONFIG_MIPI_PANEL_STA_ILI9882T) += panel-STA_ILI9882T diff --git a/src/drivers/mipi/panel-STA_2082109QFH040022_50E.c b/src/drivers/mipi/panel-STA_2082109QFH040022_50E.c new file mode 100644 index 0000000..6fe3413 --- /dev/null +++ b/src/drivers/mipi/panel-STA_2082109QFH040022_50E.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mipi/panel.h> + +struct panel_serializable_data STA_QFH040022_50E = { + .edid = { + .ascii_string = "QFH040022_50E", + .manufacturer_name = "STA", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 187097, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 346, .hso = 160, .hspw = 120, + .va = 1920, .vbl = 151, .vso = 115, .vspw = 28, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 235, + }, + }, + + .init = { + PANEL_DCS(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), + PANEL_DCS(0xE9, 0xC4), + PANEL_DCS(0xD9, 0xD1), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x33, 0xC3, 0x57, 0x36, + 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, + 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x3C, 0x33), + PANEL_DCS(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x22, 0x70, 0x3C, 0xA1, + 0x22, 0x00, 0x00, 0x00, 0x88, 0xF4), + PANEL_DCS(0xB4, 0x14, 0x16, 0x14, 0x50, 0x14, 0x50, 0x0D, 0x6A, 0x0D, + 0x6A, 0x01, 0x9E), + PANEL_DCS(0xB6, 0x34, 0x34, 0x03), + PANEL_DCS(0xB8, 0x40), + PANEL_DCS(0xE9, 0xCD), + PANEL_DCS(0xBA, 0x84), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xBC, 0x1B, 0x04), + PANEL_DCS(0xBE, 0x20), + PANEL_DCS(0xBF, 0xFC, 0xC4), + PANEL_DCS(0xC0, 0x38, 0x38, 0x22, 0x11, 0x33, 0xA0, 0x61, 0x08, 0xF5, + 0x03), + PANEL_DCS(0xE9, 0xCC), + PANEL_DCS(0xC7, 0x80), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xE9, 0xC6), + PANEL_DCS(0xC8, 0x97), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xC9, 0x00, 0x1E, 0x30, 0xD4, 0x01), + PANEL_DCS(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x16), + PANEL_DCS(0xCC, 0x02, 0x03, 0x44), + PANEL_DCS(0xE9, 0xC4), + PANEL_DCS(0xD0, 0x03), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x2C, 0xFF), + PANEL_DCS(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3B, 0x03, 0x73, 0x3B, 0x21, 0x21, 0x03, 0x03, 0x98, 0x10, + 0x1D, 0x00, 0x1D, 0x32, 0x17, 0xA1, 0x07, 0xA1, 0x43, 0x17, + 0xA6, 0x07, 0xA6, 0x00, 0x00), + PANEL_DCS(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x18, + 0x18, 0x18, 0x18, 0x2A, 0x2B, 0x1F, 0x1F, 0x1E, 0x1E, 0x24, + 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x20, + 0x21, 0x18, 0x18, 0x18, 0x18), + PANEL_DCS(0xD8, 0x02, 0xAA, 0xEA, 0xAA, 0xAA, 0x00, 0x02, 0xAA, 0xEA, + 0xAA, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + PANEL_DCS(0xE7, 0x07, 0x10, 0x10, 0x2A, 0x32, 0x9F, 0x01, 0x5A, 0x91, + 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, + 0x10, 0x33, 0x02, 0x04, 0x18, 0x01), + PANEL_DCS(0xBD, 0x01), + PANEL_DCS(0xB1, 0x01, 0x7F, 0x11, 0xFD), + PANEL_DCS(0xCB, 0x86), + PANEL_DCS(0xD2, 0x3D), + PANEL_DCS(0xE9, 0xC5), + PANEL_DCS(0xD3, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0C, 0xA1), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xD8, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x03, 0xFF, 0xFF, + 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + PANEL_DCS(0xE7, 0x02, 0x00, 0x2D, 0x01, 0x7F, 0x0F, 0x7C, 0x10, 0xA0, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00), + PANEL_DCS(0xBD, 0x02), + PANEL_DCS(0xBF, 0xF2), + PANEL_DCS(0xCB, 0x02, 0x00, 0x00, 0x10, 0x58), + PANEL_DCS(0xD2, 0x0A, 0x0A, 0x05, 0x03, 0x0A, 0x0A, 0x01, 0x03, 0x01, + 0x01, 0x05, 0x0E), + PANEL_DCS(0xE9, 0xCC), + PANEL_DCS(0xD3, 0x03, 0x1F, 0xE0, 0x11, 0x70), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xD8, 0xAB, 0xFF, 0xFF, 0xFF, 0xFF, 0xA0, 0xAB, 0xFF, 0xFF, + 0xFF, 0xFF, 0xA0), + PANEL_DCS(0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x03, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x02, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + PANEL_DCS(0xBD, 0x03), + PANEL_DCS(0xE9, 0xC6), + PANEL_DCS(0xB4, 0x03, 0xFF, 0xF8), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xD8, 0xAA, 0xAB, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAB, 0xEA, + 0xAA, 0xAA, 0xA0, 0xAA ,0xBF, 0xFF, 0xFF, 0xFE, 0xA0, 0xAA, + 0xBF ,0xFF, 0xFF, 0xFE, 0xA0, 0xAA ,0xAA, 0xAA ,0xAA ,0xAA, + 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0), + PANEL_DCS(0xE1, 0x00), + PANEL_DCS(0xBD, 0x00), + PANEL_DCS(0xE9, 0xC4), + PANEL_DCS(0xBA, 0x96), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xBD, 0x01), + PANEL_DCS(0xE9, 0xC5), + PANEL_DCS(0xBA, 0x4F), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xBD, 0x02), + PANEL_DCS(0xE9, 0xCC), + PANEL_DCS(0xBA, 0x84), + PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xBD, 0x00), + PANEL_DCS(0xB9, 0x00, 0x00, 0x00, 0x00), + + PANEL_DCS(0x11), + PANEL_DELAY(120), + PANEL_DCS(0x29), + PANEL_DELAY(5), + PANEL_END, + }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131e179b7c4420e2038ec4023f9b2f505fc6c088 Gerrit-Change-Number: 85889 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/uart: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85784?usp=email ) Change subject: drivers/uart: Replace 'unsigned long int' by 'unsigned long' ...................................................................... drivers/uart: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Change-Id: I1416a2f7d75a888dcaf0775894aced981800866f Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85784 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index a7fc346..89ec229 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -26,14 +26,14 @@ static void uart8250_tx_byte(unsigned int base_port, unsigned char data) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); outb(data, base_port + UART8250_TBR); } static void uart8250_tx_flush(unsigned int base_port) { - unsigned long int i = FIFO_TIMEOUT; + unsigned long i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); } @@ -44,7 +44,7 @@ static unsigned char uart8250_rx_byte(unsigned int base_port) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i && !uart8250_can_rx_byte(base_port)) i--; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 19677a8..fcf031e 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -46,7 +46,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_mem_can_tx_byte(base)) udelay(1); uart8250_write(base, UART8250_TBR, data); @@ -54,7 +54,7 @@ static void uart8250_mem_tx_flush(void *base) { - unsigned long int i = FIFO_TIMEOUT; + unsigned long i = FIFO_TIMEOUT; while (i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) udelay(1); } @@ -66,7 +66,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i && !uart8250_mem_can_rx_byte(base)) { udelay(1); i--; -- To view, visit https://review.coreboot.org/c/coreboot/+/85784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1416a2f7d75a888dcaf0775894aced981800866f Gerrit-Change-Number: 85784 Gerrit-PatchSet: 2 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85783?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/c/coreboot/+/85783/comment/180d2baf_08893029?us… : PS1, Line 131: } Wondering if this cast is needed -- To view, visit https://review.coreboot.org/c/coreboot/+/85783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I940528dc4f8cb9b2d441d0f0d181cccebd315255 Gerrit-Change-Number: 85783 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 08 Jan 2025 03:07:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Jarried Lin (Code Review) 08 Jan '25

08 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... soc/mediatek/mt8196: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. It takes 54 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308 mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes) TEST=Build pass and we can see the mcupm logs after reset releases. BUG=b:317009620 Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Signed-off-by: agogo.huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mcupm_plat.h A src/soc/mediatek/mt8196/mcupm.c M src/soc/mediatek/mt8196/soc.c 6 files changed, 238 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85888/1 diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 014b596..6d7ea68 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -57,4 +57,10 @@ help The file name of the MediaTek GPUEB firmware. +config MCUPM_FIRMWARE + string + default "mcupm.bin" + help + The file name of the MediaTek MCUPM firmware. + endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9bb31e1..42a4d2a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -50,7 +50,7 @@ ramstage-y += ../common/emi.c ramstage-y += gpueb.c ramstage-y += l2c_ops.c -ramstage-y += ../common/mcu.c +ramstage-y += ../common/mcu.c mcupm.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += msdc.c @@ -77,6 +77,7 @@ $(CONFIG_DPM_DM_FIRMWARE) \ $(CONFIG_DPM_PM_FIRMWARE) \ $(CONFIG_GPUEB_FIRMWARE) \ + $(CONFIG_MCUPM_FIRMWARE) \ $(CONFIG_SSPM_FIRMWARE) \ $(CONFIG_SPM_FIRMWARE) diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 3790c02..9f14b57 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -6,6 +6,7 @@ enum { MCUSYS_BASE = 0x0C000000, MCUPM_CFG_BASE = 0x0C240000, + MCUPM_SRAM_BASE = 0x0C250000, BUS_TRACE_MONITOR_BASE = 0x0D040000, IO_PHYS = 0x10000000, MFGSYS_BASE = 0x40000000, @@ -40,11 +41,13 @@ PMICSPI_MST_BASE = IO_PHYS + 0x00025000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, IFRBUS_AO_REG_BUS_BASE = IO_PHYS + 0x0002C000, + APIFRBUS_AO_BASE = IO_PHYS + 0x0002C000, GPIO_BASE = IO_PHYS + 0x0002D000, DBGSYS_AO_DEBUG_BASE = IO_PHYS + 0x00031000, APINFRA_IO_AO_DEBUG_BASE = IO_PHYS + 0x00155000, APINFRA_IO_CTRL_AO_BCRM_BASE = IO_PHYS + 0x00156000, APINFRA_IO_CTRL_AO_DEBUG_BASE = IO_PHYS + 0x00157000, + DEVAPC_INFRA_SECU_AO_BASE = IO_PHYS + 0x001C8000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, APINFRA_DRAMC_AO_DEBUG_BASE = IO_PHYS + 0x002F1000, EMI0_BASE = IO_PHYS + 0x00469000, diff --git a/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h new file mode 100644 index 0000000..8127fbe --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mcupm_plat.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_MCUPM_PLAT_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_MCUPM_PLAT_H__ + +#include <soc/addressmap.h> +#include <soc/mcupm_plat.h> +#include <types.h> + +#define MCUPM_SW_RSTN (MCUCFG_BASE + 0x00240000) +#define CLK_CFG_14 (CKSYS_BASE + 0x000000F0) + +/* + * mcusys_par_wrap config + */ +/* CPU_EB_CLK_SRC_CONFIG */ +#define CPUEB_CLK_SRC (MCUCFG_BASE + 0x000002E8) + +#define CPUEB_SPMC_STATUS (MCUCFG_BASE + 0x00000B48) +#define CPUEB_FSM_STATE_ON 0xF +#define CPUEB_FSM_STATE_OFF 0x0 +#define CPUEB_FSM_STATE_RET 0x1D +#define CPUEB_FSM_STATE_FUNC_RET 0x13 + +#define CPUEB_SPMC_SEL (MCUCFG_BASE + 0x00000B4C) + +#define MCU_PORT_SET_W1C_0 (APIFRBUS_AO_BASE + 0x00000708) +#define CPUEB_PROTECT_EN_0 BIT(8) +#define CPUEB_PROTECT_EN_1 BIT(9) +#define MCU_PORT_SET_R0_0 (APIFRBUS_AO_BASE + 0x0000070C) +#define CPUEB_PROTECT_RDY_0 BIT(8) +#define CPUEB_PROTECT_RDY_1 BIT(9) + +/* + * SPM config: + * Enable register access key, POWERON_CONFIG_EN = 0x0B160001 + */ + /* 0x1C004000 */ +#define POWERON_CONFIG_EN_MCU (SPM_BASE + 0x000) +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) +/* 1b */ +#define BCLK_CG_EN_LSB BIT(0) +/* CPUEB SPMC Control */ +/* SPM and MCUPM SPMC sideband control */ +#define SPM_MCUPM_SPMC_CON (SPM_BASE + 0x288) +/* 1'b0, SPM power state, 0: invalid, 1: valid */ +#define CPUEB_STATE_VALID BIT(0) +/* 1'b0, power state request for CPUEB */ +#define REQ_PWR_ON BIT(1) +/* 1'b0, memory retention state request for CPUEB */ +#define REQ_MEM_RET BIT(2) +/* 1'b0, spmc finish operation, 0:unfinish, 1:finish */ +#define CPUEB_STATE_FINISH_ACK BIT(31) + +/* 512K Bytes */ +#define MCUPM_SRAM_SIZE (512 * KiB) + +/* GPR */ +#define MCUPM_GPR_SIZE 0x00000070 /* 112 Bytes */ +/* IPI */ +#define IPI_NUMBER 16 +#define IPI_MBOX_TOTAL IPI_NUMBER + +/* MCUPM REG */ +#define MCUPM_CFGREG_SW_RSTN_SW_RSTN BIT(0) +#define MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK (BIT(1)|BIT(2)|BIT(3)|BIT(4)) + +#define DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0 (DEVAPC_INFRA_SECU_AO_BASE + 0x0300) +#define REPLACE_15 BIT(15) +#define POLLING_MCU_TIME 10 +#define POLLING_ACK_TIME 10 +#define ABNORMALBOOT_REG_STATUS 0x0 +#define WARMBOOT_REG_STATUS 0x0 +#define MCUPM_RSTN_RESET 0x1F +#define MCUPM_RSTN_RSTN_INIT 0x0 + +#define CPUEB_SPMC_STATUS_OFFSET 3 +#define CPUEB_SPMC_STATUS_MASK 0x3F + +#define SRAM_GPR_SIZE 0x4 /* 4 Bytes */ + +#define MBOX_SLOT_SIZE 0x00000004 +#define SRAM_SLOT_SIZE 0x00000014 /* 0x14 = 20 slots = 20*4Bytes = 80 Bytes */ +#define PIN_S_SIZE SRAM_SLOT_SIZE +#define PIN_R_SIZE SRAM_SLOT_SIZE +#define MBOX_TABLE_SIZE (PIN_S_SIZE + PIN_R_SIZE) + +#define GPR_BASE_ADDR_MCU(x) (MCUPM_SRAM_BASE + \ + MCUPM_SRAM_SIZE - \ + (IPI_MBOX_TOTAL * MBOX_TABLE_SIZE * MBOX_SLOT_SIZE) - \ + MCUPM_GPR_SIZE + \ + ((x) * SRAM_GPR_SIZE)) /* 0x1000BC7C */ + +#define ABNORMALBOOT_REG GPR_BASE_ADDR_MCU(1) +#define WARMBOOT_REG GPR_BASE_ADDR_MCU(23) + +#endif /* __SOC_MEDIATEK_MT8196_INCLUDE_SOC_MCUPM_PLAT_H__ */ diff --git a/src/soc/mediatek/mt8196/mcupm.c b/src/soc/mediatek/mt8196/mcupm.c new file mode 100644 index 0000000..1cad4c9 --- /dev/null +++ b/src/soc/mediatek/mt8196/mcupm.c @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <device/mmio.h> +#include <soc/mcu_common.h> +#include <soc/mcupm.h> +#include <soc/mcupm_plat.h> +#include <soc/symbols.h> +#include <stdlib.h> + +static int eb_sleep_protect(void) +{ + /* Set MCU_PORT_SET_W1C_0[9:8] = 2'b11 */ + setbits32p(MCU_PORT_SET_W1C_0, CPUEB_PROTECT_EN_0 | CPUEB_PROTECT_EN_1); + + /* Polling MCU_PORT_SET_R0_0[9:8] = 2'b00 */ + if (!retry(POLLING_MCU_TIME, + (read32p(MCU_PORT_SET_R0_0) & + (CPUEB_PROTECT_RDY_0 | CPUEB_PROTECT_RDY_1)) == 0, udelay(1))) { + printk(BIOS_WARNING, + "[EB_SPMC] Polling MCU_PORT_SET_R0_0 timeout, %#x\n", + read32p(MCU_PORT_SET_R0_0)); + return -1; + } + + return 0; +} + +static int eb_spmc_spm(void) +{ + /* Unlock SPM POWERON_CONFIG_EN */ + setbits32p(POWERON_CONFIG_EN_MCU, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* set REQ_PWR_ON = 1 and REQ_MEM_RET = 0 */ + setbits32p(SPM_MCUPM_SPMC_CON, REQ_PWR_ON); + + clrbits32p(SPM_MCUPM_SPMC_CON, REQ_MEM_RET); + + /* set CPUEB_STATE_VALID = 1 */ + setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); + + /* polling CPUEB_STATE_FINISH_ACK = 1 */ + if (!retry(POLLING_ACK_TIME, + (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == + CPUEB_STATE_FINISH_ACK, udelay(1))) { + printk(BIOS_WARNING, + "[EB_SPMC] Polling ACK timeout, %#x\n", + read32p(SPM_MCUPM_SPMC_CON)); + return -1; + } + + /* set CPUEB_STATE_VALID = 0 */ + clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); + + /* polling CPUEB_STATE_FINISH_ACK = 0 */ + if (!retry(POLLING_ACK_TIME, + (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != + CPUEB_STATE_FINISH_ACK, udelay(1))) { + printk(BIOS_WARNING, + "[EB_SPMC] Polling ACK timeout, %#x\n", + read32p(SPM_MCUPM_SPMC_CON)); + return -1; + } + + eb_sleep_protect(); + + return 0; +} + +static int eb_spmc(void) +{ + uint32_t spmc_status = (read32p(CPUEB_SPMC_STATUS) >> CPUEB_SPMC_STATUS_OFFSET) & + CPUEB_SPMC_STATUS_MASK; + int ret = 0; + + switch (spmc_status) { + case CPUEB_FSM_STATE_OFF: + case CPUEB_FSM_STATE_ON: + case CPUEB_FSM_STATE_RET: + case CPUEB_FSM_STATE_FUNC_RET: + printk(BIOS_INFO, "%s: spmc_status = %#x\n", __func__, spmc_status); + ret = eb_spmc_spm(); + break; + default: + printk(BIOS_ERR, "%s [EB_SPMC] EB SPMC in wrong state, spmc_status = %#x\n", + __func__, spmc_status); + ret = -1; + break; + } + + return ret; +} + +static void reset_mcupm(struct mtk_mcu *mcu) +{ + /* Clear abnormal boot register */ + write32p(ABNORMALBOOT_REG, ABNORMALBOOT_REG_STATUS); + write32p(WARMBOOT_REG, WARMBOOT_REG_STATUS); + write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RESET); + + write32p(MCUPM_SW_RSTN, MCUPM_CFGREG_SW_RSTN_SW_RSTN | MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK); +} + +static struct mtk_mcu mcupm = { + .firmware_name = CONFIG_MCUPM_FIRMWARE, + .run_address = (void *)MCUPM_SRAM_BASE, + .reset = reset_mcupm, +}; + +void mcupm_init(void) +{ + mcupm.load_buffer = _dram_dma; + mcupm.buffer_size = REGION_SIZE(dram_dma); + + /* Set CPUEB as secure master */ + printk(BIOS_INFO, "Before: DEVAPC_MCUPM = %#x\n", + read32p(DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0)); + setbits32p(DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0, REPLACE_15); + printk(BIOS_INFO, "After: DEVAPC_MCUPM = %#x\n", + read32p(DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0)); + + if (eb_spmc() != 0) + die("%s() eb sram power on failed\n", __func__); + write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RSTN_INIT); + if (mtk_init_mcu(&mcupm)) + die("%s() failed\n", __func__); +} diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 6a78d1c..1f1da7c 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -6,6 +6,7 @@ #include <soc/dramc_info.h> #include <soc/emi.h> #include <soc/gpueb.h> +#include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/pcie.h> #include <soc/sspm.h> @@ -35,6 +36,7 @@ mtk_mmu_disable_l2c_sram(); sspm_init(); gpueb_init(); + mcupm_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: arch/x86: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85782?usp=email ) Change subject: arch/x86: Replace 'unsigned long int' by 'unsigned long' ...................................................................... arch/x86: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Cc: "Jérémy Compostella" <jeremy.compostella(a)intel.com> Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85782 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/memset.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 142dda3..4ab07ed 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -12,7 +12,7 @@ void *memset(void *dstpp, int c, size_t len) { int d0; - unsigned long int dstp = (unsigned long int)dstpp; + unsigned long dstp = (unsigned long)dstpp; #if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Gerrit-Change-Number: 85782 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85786?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) File util/cbfstool/flashmap/fmap.c: https://review.coreboot.org/c/coreboot/+/85786/comment/20b406a9_219ef668?us… : PS1, Line 99: unsigned long offset = -1; If it is unsigned, how it is = -1 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 08 Jan 2025 02:56:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the argument type of MT6363
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85839?usp=email ) Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363 ...................................................................... soc/mediatek/mt8196: Correct the argument type of MT6363 Correct the argument type of the mt6363_sdmadc_read API and the return value type of the mt6363_read16 API. TEST=Build pass BUG=b:317009620 Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85839 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/boardid.c M src/soc/mediatek/common/include/soc/mt6363.h M src/soc/mediatek/common/include/soc/mt6363_sdmadc.h M src/soc/mediatek/common/mt6363.c M src/soc/mediatek/common/mt6363_sdmadc.c 5 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index e3e0979..fc0230d 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -38,7 +38,7 @@ static uint32_t get_adc_index(unsigned int channel) { - int value; + u32 value; mt6363_sdmadc_read(channel, &value, SDMADC_OPEN, AUXADC_VAL_PROCESSED); assert(channel < ARRAY_SIZE(adc_voltages)); diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h index 19b23d4..4659119 100644 --- a/src/soc/mediatek/common/include/soc/mt6363.h +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -108,7 +108,7 @@ void mt6363_enable_vram_digrf(bool enable); void mt6363_enable_vram_mdfe(bool enable); void mt6363_init_pmif_arb(void); -u32 mt6363_read16(u32 reg); +u16 mt6363_read16(u32 reg); void mt6363_write8(u32 reg, u8 reg_val); void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); void mt6363_init_setting(void); diff --git a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h index ae990c9..8735824 100644 --- a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h +++ b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h @@ -84,7 +84,7 @@ } sdmadc_hw_info; }; -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, enum sdmadc_pures pures, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type); #endif /* __MT6363_SDMADC_H__ */ diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 20ef9f0..b16f6b1 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -25,7 +25,7 @@ }; static struct pmif *pmif_arb; -u32 mt6363_read16(u32 reg) +u16 mt6363_read16(u32 reg) { u16 rdata = 0; diff --git a/src/soc/mediatek/common/mt6363_sdmadc.c b/src/soc/mediatek/common/mt6363_sdmadc.c index eb4b978..647423d 100644 --- a/src/soc/mediatek/common/mt6363_sdmadc.c +++ b/src/soc/mediatek/common/mt6363_sdmadc.c @@ -61,11 +61,11 @@ _Static_assert(ARRAY_SIZE(mt6363_sdmadc_chan_specs) == AUXADC_CHAN_MAX, "Wrong array size for mt6363_sdmadc_chan_specs"); -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type) { u8 wdata; - u32 regval; + u16 regval; u32 elapsed = 0; const struct auxadc_chan_spec *chan; -- To view, visit https://review.coreboot.org/c/coreboot/+/85839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Gerrit-Change-Number: 85839 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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