coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/intel/adl: Handle critical low battery early in romstage
by Subrata Banik (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86227?usp=email ) Change subject: soc/intel/adl: Handle critical low battery early in romstage ...................................................................... soc/intel/adl: Handle critical low battery early in romstage This commit implements early handling of critical low battery conditions in the romstage for Alder Lake platforms. A message is displayed to the user via ux_inform_user_of_poweroff_operation. A short delay is introduced to allow the user to see the message. A low battery event is logged. The system is shut down via the Chrome EC. This early handling prevents the system from proceeding with boot (while performing firmware update) if the battery is critically low and ensures a clean shutdown. This is particularly important for ChromeOS devices. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86227/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 4a03b74..0f02818 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -5,12 +5,15 @@ #include <cpu/x86/msr.h> #include <cpu/intel/common/common.h> #include <cpu/intel/cpu_ids.h> +#include <delay.h> #include <device/device.h> #include <drivers/wifi/generic/wifi.h> +#include <ec/google/chromeec/ec.h> #include <elog.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <gpio.h> +#include <halt.h> #include <intelbasecode/debug_feature.h> #include <intelblocks/cpulib.h> #include <intelblocks/cse.h> @@ -413,6 +416,18 @@ debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode); } +static void is_early_critical_shutdown_needed(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_below_critical_threshold()) { + ux_inform_user_of_poweroff_operation("critical battery"); + /* Allow user to notice the low battery indicator before poweroff */ + delay(3); + elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN); + /* Send Shutdown command to EC */ + google_chromeec_reboot(EC_REBOOT_COLD_AP_OFF,0); + } +} + static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, FSPM_ARCH_UPD *arch_upd) { @@ -427,6 +442,9 @@ * user with an on-screen text message. */ if (!arch_upd->NvsBufferPtr) { + if (CONFIG(CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN_EARLY)) + is_early_critical_shutdown_needed(); + esol_required = true; name = "memory training"; elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); -- To view, visit https://review.coreboot.org/c/coreboot/+/86227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2 Gerrit-Change-Number: 86227 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add platform callback for critical shutdown
by Subrata Banik (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Ronak Kanabar. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86226?usp=email ) Change subject: drivers/intel/fsp2_0: Add platform callback for critical shutdown ...................................................................... drivers/intel/fsp2_0: Add platform callback for critical shutdown This commit adds the platform_is_critical_shutdown_needed callback to the FSP API. This allows platforms to integrate low-battery handling logic directly into the FSP silicon initialization process. By checking for critical conditions (e.g., low battery) within this callback after FSP silicon initialization, the platform can initiate a controlled shutdown before proceeding with further boot stages, preventing abrupt shutdowns later in the boot process. BUG=b:339673254 TEST=Verified low battery boot event logging. Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/86226/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 971be0d..8285948 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -50,6 +50,13 @@ /* Callbacks for SoC/Mainboard specific overrides */ void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index); void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index); +/* + * Platform specific callbacks for power-off handling. + * + * These callbacks allow the platform to determine if a power-off is + * necessary due to various reasons, such as low battery detection. + */ +void platform_is_critical_shutdown_needed(void); /* Check if MultiPhase Si Init is enabled */ bool fsp_is_multi_phase_init_enabled(void); /* diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1caf00f..6ef9ba4 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -29,6 +29,11 @@ /* Leave for the SoC/Mainboard to implement if necessary. */ } +void __weak platform_is_critical_shutdown_needed(void) +{ + /* Platform specific callbacks for power-off handling. */ +} + /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 * has multiple stages as below. */ @@ -254,6 +259,9 @@ fsps_load(); do_silicon_init(&fsps_hdr); + if (CONFIG(CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN)) + platform_is_critical_shutdown_needed(); + if (CONFIG(CACHE_MRC_SETTINGS) && CONFIG(FSP_NVS_DATA_POST_SILICON_INIT)) save_memory_training_data(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0 Gerrit-Change-Number: 86226 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>

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[S] Change in coreboot[main]: vc/google/chromeos: Add low battery indicator screen
by Subrata Banik (Code Review) 30 Jan '25

30 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: vc/google/chromeos: Add low battery indicator screen ...................................................................... vc/google/chromeos: Add low battery indicator screen This commit adds support for displaying a low battery indicator screen in the firmware. This screen is displayed when the system detects a critically low battery condition. The screen displays a logo and can be configured with a custom path. An option to display an early low battery indicator in text mode is also included. This early indicator can defer the firmware update. The implementation relies on FSP-S UPD parameters for rendering low battery logo over display. This feature is controlled by the CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN Kconfig option. BUG=b:339673254 TEST=Able to capture the eventlog for low battery boot event. Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.mk M src/vendorcode/google/chromeos/splash.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/86225/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 60f48fe..fe9f309 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -102,6 +102,36 @@ depends on CHROMEOS_FW_SPLASH_SCREEN default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" +config CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN + bool "Display Low Battery Indicator in firmware" + default n + select BMP_LOGO + select HAVE_CUSTOM_BMP_LOGO + help + If enabled, this option displays a low battery indicator screen + in the firmware. This screen can be used to warn the user + that the battery is low and that they should plug in the + device. + + This option requires that the system have a display and that + the BMP_LOGO and HAVE_CUSTOM_BMP_LOGO options are also enabled. + +config CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN_EARLY + bool "Display Early Low Battery Indicator in firmware" + depends on CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN + help + If enabled, this option displays a low battery indicator early + in text mode in the firmware and defer the firmware update. + This screen can be used to warn the user that the battery is low + and that they should plug in the device. + + Don't select if not sure. + +config CHROMEOS_LOW_BATTERY_INDICATOR_LOGO_PATH + string "Path to ChromeOS low battery logo file" + depends on CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" + config CHROMEOS_ENABLE_ESOL def_bool FSP_UGOP_EARLY_SIGN_OF_LIFE || MAINBOARD_HAS_EARLY_LIBGFXINIT help diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk index 44d4d2b..3147102 100644 --- a/src/vendorcode/google/chromeos/Makefile.mk +++ b/src/vendorcode/google/chromeos/Makefile.mk @@ -39,3 +39,8 @@ cb_plus_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEBOOK_PLUS_LOGO_PATH)) cb_plus_logo.bmp-type := raw cb_plus_logo.bmp-compression := $(BMP_LOGO_COMPRESS_FLAG) + +cbfs-files-$(CONFIG_CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN) += low_battery_logo.bmp +low_battery_logo.bmp-file := $(call strip_quotes,$(CONFIG_CHROMEOS_LOW_BATTERY_INDICATOR_LOGO_PATH)) +low_battery_logo.bmp-type := raw +low_battery_logo.bmp-compression := $(BMP_LOGO_COMPRESS_FLAG) diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c index f63f526..0c7cba7 100644 --- a/src/vendorcode/google/chromeos/splash.c +++ b/src/vendorcode/google/chromeos/splash.c @@ -1,10 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootsplash.h> +#include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +static bool chromeos_render_low_battery_logo(void) +{ + if (!CONFIG(CHROMEOS_LOW_BATTERY_INDICATOR_SCREEN) || !CONFIG(EC_GOOGLE_CHROMEEC)) + return false; + + return google_chromeec_is_below_critical_threshold(); +} + const char *bmp_logo_filename(void) { + if (chromeos_render_low_battery_logo()) + return "low_battery_logo.bmp"; + if (chromeos_device_branded_plus_hard()) return "cb_plus_logo.bmp"; else if (chromeos_device_branded_plus_soft()) -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/adl: Display low battery message on screen
by Subrata Banik (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86224?usp=email ) Change subject: soc/intel/adl: Display low battery message on screen ...................................................................... soc/intel/adl: Display low battery message on screen This commit adds a function ux_inform_user_of_poweroff_operation to display a message on the screen when the system is powering off due to critically low battery. The message is centered on the screen and displays a localized string "Battery critically low. Shutting down". If no localized string is found, a default English message is displayed. This implementation rely on CHROMEOS_ENABLE_ESOL Kconfig which is use to render text message for early sign-off life. BUG=b:339673254 TEST=Able to capture the eventlog for low battery boot event. Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/alderlake/romstage/ux.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86224/1 diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c index 0fb73c18..b79298d 100644 --- a/src/soc/intel/alderlake/romstage/ux.c +++ b/src/soc/intel/alderlake/romstage/ux.c @@ -34,3 +34,26 @@ timestamp_add_now(TS_ESOL_END); return true; } + +bool ux_inform_user_of_poweroff_operation(const char *name) +{ + timestamp_add_now(TS_ESOL_START); + + if (!CONFIG(CHROMEOS_ENABLE_ESOL) || + !early_graphics_init()) { + timestamp_add_now(TS_ESOL_END); + return false; + } + + printk(BIOS_INFO, "Informing user on-display of %s.\n", name); + + const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC); + /* No localized text found; fallback to built-in English. */ + if (!text) + text = "Battery critically low. Shutting down"; + vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE, + (const unsigned char *)text); + ux_locales_unmap(); + timestamp_add_now(TS_ESOL_END); + return true; +} diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h index 14c10e7..c556c63 100644 --- a/src/soc/intel/alderlake/romstage/ux.h +++ b/src/soc/intel/alderlake/romstage/ux.h @@ -4,5 +4,6 @@ #define _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ bool ux_inform_user_of_update_operation(const char *name); +bool ux_inform_user_of_poweroff_operation(const char *name); #endif /* _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d Gerrit-Change-Number: 86224 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: util/cbfstool/eventlog: Add low battery event type
by Subrata Banik (Code Review) 30 Jan '25

30 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86223?usp=email ) Change subject: util/cbfstool/eventlog: Add low battery event type ...................................................................... util/cbfstool/eventlog: Add low battery event type This commit adds a new event type, `ELOG_TYPE_LOW_BATTERY_INDICATOR`, to the event log. This event is logged when the system boots due to a low battery condition. It includes the reason for the shutdown, currently only supporting "Poweroff: Low Battery". BUG=b:339673254 TEST=Able to capture the eventlog for low battery boot event. Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M util/cbfstool/eventlog.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/86223/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index f7dc4a1..01f97f6 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -389,6 +389,9 @@ #define ELOG_FW_POST_RAM_CSE_SYNC 0x1 #define ELOG_FW_CSE_SYNC_AT_PAYLOAD 0x2 +#define ELOG_TYPE_LOW_BATTERY_INDICATOR 0xbe +#define ELOG_FW_ISSUE_SHUTDOWN 0x0 + /* Only the 7-LSB are used for size */ #define ELOG_MAX_EVENT_SIZE 0x7F diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 4746670..c4e6b64 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -170,6 +170,7 @@ {ELOG_TYPE_PSR_DATA_LOST, "PSR data lost"}, {ELOG_TYPE_FW_SPLASH_SCREEN, "Firmware Splash Screen"}, {ELOG_TYPE_FW_CSE_SYNC, "Firmware CSE sync"}, + {ELOG_TYPE_LOW_BATTERY_INDICATOR, "Low Battery Boot "}, {ELOG_TYPE_EOL, "End of log"}, }; @@ -491,6 +492,11 @@ {0, NULL}, }; + static const struct valstr low_battery_path_types[] = { + {ELOG_FW_ISSUE_SHUTDOWN, "Poweroff: Low Battery"}, + {0, NULL}, + }; + size_t elog_type_to_min_size[] = { [ELOG_TYPE_LOG_CLEAR] = sizeof(uint16_t), [ELOG_TYPE_BOOT] = sizeof(uint32_t), @@ -513,6 +519,7 @@ [ELOG_TYPE_PSR_DATA_BACKUP] = sizeof(uint8_t), [ELOG_TYPE_FW_SPLASH_SCREEN] = sizeof(uint8_t), [ELOG_TYPE_FW_CSE_SYNC] = sizeof(uint8_t), + [ELOG_TYPE_LOW_BATTERY_INDICATOR] = sizeof(uint8_t), [0xff] = 0, }; @@ -684,6 +691,11 @@ eventlog_printf("%s", val2str(*cse_event, cse_sync_path_types)); break; } + case ELOG_TYPE_LOW_BATTERY_INDICATOR: { + const uint8_t *sol_event = event_get_data(event); + eventlog_printf("%s", val2str(*sol_event, late_sol_path_types)); + break; + } default: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/86223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a Gerrit-Change-Number: 86223 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant
by Keith Hui (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Keith Hui. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85768?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant ...................................................................... mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant Based on p8z77-v, with adjusted overridetree, GPIO, GMA, HDA verbs and USB port config based on boardview and vendor firmware image. It builds, but not hardware tested. Unlike most other variants, this one allows use of MRC raminit, if for testing. It has no serial port, but the code describes a possible hardware hack to get one working to receive console output. A debug port allows access to LPC bus. Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/sabertooth_z77.md M Documentation/mainboard/index.md A configs/config.asus_sabertooth_z77_mrc_bin M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb 14 files changed, 803 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85768/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Gerrit-Change-Number: 85768 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/cmn/cnvi: Change the Power Resource to S0
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers. Hello Cliff Huang, Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86195?usp=email to look at the new patch set (#2). Change subject: soc/intel/cmn/cnvi: Change the Power Resource to S0 ...................................................................... soc/intel/cmn/cnvi: Change the Power Resource to S0 This resource is applicable to S0, as it can be used to reset the wireless, so change it from S5. Change-Id: I36cc7cd9353b249403da12e1c99734aeea70edb9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/86195/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36cc7cd9353b249403da12e1c99734aeea70edb9 Gerrit-Change-Number: 86195 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: Bill, since I also removed the PP/OD setting around GPIO bank 7 which overlaps with the 3 reset output pins, please watch for regressions around rebooting. File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/56656349_9d902c75?us… : PS2, Line 77: {7, 34, 20, -1} > The `overridetree.cb` still specifies `drq 0xe4 = 0xfc` for `device pnp 2e. […] Fix in. Thanks for the catch. Goes to show that I need more sleep. -.- -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Jan 2025 14:59:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: Revert "mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration"
by Matt DeVillier (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86222?usp=email ) Change subject: Revert "mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3da0d9873535e9287494f32563bc42ca4d4f9579 Gerrit-Change-Number: 86222 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 30 Jan 2025 14:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Revert "mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration"
by Matt DeVillier (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86221?usp=email ) Change subject: Revert "mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaab736bf3dd859b00b0681d9dbcc6273d8000d63 Gerrit-Change-Number: 86221 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 30 Jan 2025 14:56:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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