coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Matt DeVillier (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/76582?usp=email ) Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76582/comment/61e8e7b1_de649c27?us… : PS14, Line 10: that than? -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 07 Jan 2025 21:17:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Add a CMOS option to disable the GNA
by Matt DeVillier (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85703?usp=email ) Change subject: mb/starlabs/*: Add a CMOS option to disable the GNA ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85703/comment/53f10d5f_8c0eae5d?us… : PS10, Line 9: the which? -- To view, visit https://review.coreboot.org/c/coreboot/+/85703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Gerrit-Change-Number: 85703 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 07 Jan 2025 21:16:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common: Read core scaling factors at runtime support
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85553?usp=email ) Change subject: soc/intel/common: Read core scaling factors at runtime support ...................................................................... soc/intel/common: Read core scaling factors at runtime support Starting with Lunar Lake, the scaling factor information is centralized in the power control unit (PCU) firmware. In order to keep all firmware in sync, it is recommended to read the scaling factors from the PCU firmware instead of using hard-coded values. This commit adds a new Kconfig option, CONFIG_SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS, to allow SoC specific code to specify its own function to read the core scaling factors. When this option is enabled, the soc_read_core_scaling_factors() function from the SoC specific code is used to read the core scaling factors instead of using the statically defined values CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR. Change-Id: Icdf47e17cc5a6d042f3c5f90cf811fccd6c1ed9b Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85553 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Cliff Huang <cliff.huang(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 31 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Cliff Huang: Looks good to me, but someone else must approve Pranava Y N: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 827bedd..df354c7 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -54,6 +54,15 @@ help Defines hybrid CPU specific ACPI helper functions. +config SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS + bool + depends on SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + help + Core performance and efficient scaling factors are read at runtime + using the soc_read_core_scaling_factors() function instead of using + statically defined values SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and + SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR. + config SOC_INTEL_UFS_OCP_TIMER_DISABLE bool help diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 68abba7..36905fe 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -113,18 +113,27 @@ static void acpi_get_cpu_nomi_perf(u16 *eff_core_nom_perf, u16 *perf_core_nom_perf) { u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + static u16 performance, efficient; - _Static_assert(CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR must not be zero"); - _Static_assert(CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR must not be zero"); - *perf_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR) / 100); + if (!performance) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS)) { + soc_read_core_scaling_factors(&performance, &efficient); + } else { + performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; + efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; + } + } - *eff_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR) / 100); + *perf_core_nom_perf = (u16)((max_non_turbo_ratio * performance) / 100); + *eff_core_nom_perf = (u16)((max_non_turbo_ratio * efficient) / 100); } static u16 acpi_get_cpu_nominal_freq(void) diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index fa32092..9ec8984 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -20,6 +20,13 @@ unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current); +/* + * Read the performance and efficient core ratios. + * This is to be implemented by the SoC specific code if + * SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS is selected. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient); + /* Generates ACPI code to define _CPC control method */ void acpigen_write_CPPC_hybrid_method(int core_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/85553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdf47e17cc5a6d042f3c5f90cf811fccd6c1ed9b Gerrit-Change-Number: 85553 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: cpu/x86/topology: Add module_id to CPU topology
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85577?usp=email ) Change subject: cpu/x86/topology: Add module_id to CPU topology ...................................................................... cpu/x86/topology: Add module_id to CPU topology This commit adds a module_id field to the cpu_topology structure. This field is used to identify the module that a CPU is located on. This information is useful for power management and other purposes. Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85577 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/topology.c M src/include/device/path.h 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index b2fd202..58e71fc 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -116,6 +116,7 @@ } apic_fields[] = { { LEVEL_TYPE_SMT, &cpu->path.apic.thread_id }, { LEVEL_TYPE_CORE, &cpu->path.apic.core_id }, + { LEVEL_TYPE_MODULE, &cpu->path.apic.module_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id } }; diff --git a/src/include/device/path.h b/src/include/device/path.h index 8e9ec3b..fdc2f44 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -81,6 +81,7 @@ unsigned int node_id; unsigned int core_id; unsigned int thread_id; + unsigned int module_id; unsigned char core_type; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27 Gerrit-Change-Number: 85577 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelp2m/patform/cnl: Add unit tests
by Daniel Maslowski (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Alicja Michalska, David Hendricks, Maxim Polyakov. Daniel Maslowski has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85548?usp=email ) Change subject: intelp2m/patform/cnl: Add unit tests ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb0b6506a07b96903e6bc7994e5f97d483d0a330 Gerrit-Change-Number: 85548 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 20:27:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/intelp2m/fields: Add unit tests
by Daniel Maslowski (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Alicja Michalska, David Hendricks, Maxim Polyakov. Daniel Maslowski has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/68673?usp=email ) Change subject: util/intelp2m/fields: Add unit tests ...................................................................... Patch Set 19: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Gerrit-Change-Number: 68673 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 20:25:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Add a CMOS option to disable the GNA
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85703?usp=email ) Change subject: mb/starlabs/*: Add a CMOS option to disable the GNA ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85703/comment/1d6627b1_5c40ea66?us… : PS9, Line 7: mb/starlabs/*: Add a CMOS option to disable the GNA > nit: short explanation of what the GNA is? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Gerrit-Change-Number: 85703 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 20:22:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/*: Add a CMOS option to disable the GNA
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85703?usp=email to look at the new patch set (#10). Change subject: mb/starlabs/*: Add a CMOS option to disable the GNA ...................................................................... mb/starlabs/*: Add a CMOS option to disable the GNA Add an option, the defaults to disabled, to control whether the GNA (Gaussian Neural Accelerator) is enabled. This is a device that designed to handle AI tasks. Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/byte_adl/cmos.default M src/mainboard/starlabs/byte_adl/cmos.layout M src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/starlabs/starbook/variants/rpl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/starlabs/starfighter/cmos.default M src/mainboard/starlabs/starfighter/cmos.layout M src/mainboard/starlabs/starfighter/variants/rpl/devtree.c M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 14 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85703/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Gerrit-Change-Number: 85703 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/76582?usp=email ) Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76582/comment/79e50b26_dd294d61?us… : PS13, Line 9: rather : that option. > can you clarify? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 20:20:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#14). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather that CMOS. However, some still need to stay in CMOS, so that they can be accessed via ACPI. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 141 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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coreboot-gerrit January 2025