coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Angel Pons, Keith Hui. Hello Bill XIE, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85413?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... mb/asus/p8z77-v: Attempt to correctly route PCIe lanes Bill Xie documented in his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. Another one needs to be added later to enable users to allocate all lanes to PCIEX16_3 and make it x4. 3. Add code to bootblock to check the PCHSTRP9 soft strap and whether (1) is true. There is a sanity check to warn of a PCIe configuration that is not valid on this board. 4. Based on (1) and (2), program SIO GPIO5 as appropriate. Remove all GPIO5 settings from devicetree so this code has full control. Changing PCIEX16_3 from x1 to x4 (and vice versa) requires changing PCHSTRP9 in the SPI flash descriptor. How coreboot can manage this is TBD. This is based on boardview only, and is untested because I have no hardware. Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb 5 files changed, 120 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/fatcat/variants/fatcat: Enable BT audio offload
by Uday Bhat (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Naveen M, Pranava Y N, Subrata Banik. Uday Bhat has posted comments on this change by Uday Bhat. ( https://review.coreboot.org/c/coreboot/+/86121?usp=email ) Change subject: mb/google/fatcat/variants/fatcat: Enable BT audio offload ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86121/comment/ca4b3bea_edabe777?us… : PS1, Line 12: I2S and soundwire > I see that the pads are configured in case of HDA as well, so I was just wondering BT offload is not enabled for HDA till now (not even in previous platforms). Hence, disabled these pads for HDA File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/86121/comment/5f460bf1_4b2d0eaa?us… : PS1, Line 88: static const struct pad_config bt_i2s_enable_pads[] = { > Disable these pads in `AUDIO_NONE` configuration? Done https://review.coreboot.org/c/coreboot/+/86121/comment/8bd35afe_d6d16913?us… : PS1, Line 578: else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) { > > `else should follow close brace '}'` […] Done File src/mainboard/google/fatcat/variants/fatcat/variant.c: https://review.coreboot.org/c/coreboot/+/86121/comment/86f0f3fe_45f218ef?us… : PS1, Line 17: printk(BIOS_INFO, "Configure BT audio offload config.\n"); > This log message seems redundant. Acknowledged https://review.coreboot.org/c/coreboot/+/86121/comment/51ce932c_9bb29698?us… : PS1, Line 24: config->cnvi_bt_audio_offload = true; > Shouldn't setting this also depend on the `AUDIO` configs? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id68667d674386cf9e6abc066a4637ee055a967f3 Gerrit-Change-Number: 86121 Gerrit-PatchSet: 2 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 30 Jan 2025 12:31:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat/variants/fatcat: Enable BT audio offload
by Uday Bhat (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Naveen M, Uday Bhat. Hello Jayvik Desai, Kapil Porwal, Naveen M, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86121?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Naveen M, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat/variants/fatcat: Enable BT audio offload ...................................................................... mb/google/fatcat/variants/fatcat: Enable BT audio offload vGPIO configs are configured to enable SSP2 for BT audio offload. BUG=b:391771159 Test=Verified BT offload with I2S and soundwire configuration Change-Id: Id68667d674386cf9e6abc066a4637ee055a967f3 Signed-off-by: Uday M Bhat <uday.m.bhat(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/variant.c 2 files changed, 62 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86121/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id68667d674386cf9e6abc066a4637ee055a967f3 Gerrit-Change-Number: 86121 Gerrit-PatchSet: 2 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com>

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[S] Change in coreboot[main]: payloads/external/iPXE: introduce support for named configurations
by Krystian Hebel (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Felix Singer, Filip Lewiński, Martin L Roth, Michał Kopeć. Krystian Hebel has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82041?usp=email ) Change subject: payloads/external/iPXE: introduce support for named configurations ...................................................................... Patch Set 7: Code-Review-1 (1 comment) Patchset: PS7: Doesn't build without specifying named config: ``` Switched to a new branch 'coreboot' Checking named config directory: named-configs/ Applying named configuration: cp: cannot stat 'named-configs//*': No such file or directory make[1]: *** [Makefile:41: apply_named_config] Error 1 make: *** [payloads/external/Makefile.mk:372: payloads/external/iPXE/ipxe/ipxe.rom] Error 2 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf7c2d9e4407035bfdf0115f4628f23b38272656 Gerrit-Change-Number: 82041 Gerrit-PatchSet: 7 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Thu, 30 Jan 2025 12:20:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: payloads/external/Makefile.mk: Update linuxboot warning
by Elyes Haouas (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Martin L Roth, Maximilian Brune. Elyes Haouas has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/85957?usp=email ) Change subject: payloads/external/Makefile.mk: Update linuxboot warning ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: - Use of strip: If the variable contains only whitespace (e.g., " "), ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH),"") would not catch it, but ifeq ($(strip $(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH)),) would. - use of ":=" is for immediate evaluation what's about : "ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),y) ifeq ($(strip $(CONFIG_LINUXBOOT_CROSS_COMPILE_PATH)),) # No custom toolchain specified, use coreboot's cross toolchain CONFIG_LINUXBOOT_CROSS_COMPILE_PATH := $(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y)) endif else ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y) # Print a warning that we are using the host toolchain $(warning "Using host toolchain to build LinuxBoot") endif endif " ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5008d685c52c1d4e0d7eba44c964c51a2a6f99c3 Gerrit-Change-Number: 85957 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 30 Jan 2025 12:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/craaskov: Add/select VBT
by Eric Lai (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86214?usp=email ) Change subject: mb/google/brya/var/craaskov: Add/select VBT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Gerrit-Change-Number: 86214 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 30 Jan 2025 11:29:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/*: Correct config for SATA DEVSLP GPIO
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86186?usp=email ) Change subject: mb/starlabs/*: Correct config for SATA DEVSLP GPIO ...................................................................... mb/starlabs/*: Correct config for SATA DEVSLP GPIO On boards that do not use SATA, this should be connected. For boards that do use it, it should be NF5. Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/mtl/gpio.c M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c 4 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index f4d7ab0..35d9489 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -362,7 +362,7 @@ /* H12: Not Connected */ PAD_NC(GPP_H12, NONE), /* H13: PCH M.2 SSD Device Sleep */ - PAD_CFG_GPO(GPP_H13, 0, PLTRST), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), /* H14: Not Connected */ PAD_NC(GPP_H14, NONE), /* H15: DDPB Control Clock */ diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index 21821be..77be325 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -361,7 +361,7 @@ /* H12: Not Connected */ PAD_NC(GPP_H12, NONE), /* H13: PCH M.2 SSD Device Sleep */ - PAD_CFG_GPO(GPP_H13, 0, PLTRST), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), /* H14: Not Connected */ PAD_NC(GPP_H14, NONE), /* H15: DDPB Control Clock */ diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index b3ed9e2..fd4a090 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -202,6 +202,7 @@ /* E03: */ PAD_NC(GPP_E03, NONE), /* E04: M.2_SSD_DEVSLP0 */ + PAD_NC(GPP_E04, NONE), /* E05: */ PAD_NC(GPP_E05, NONE), /* E06: JTAG ODT diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index e0e6164..18c5651 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -358,7 +358,7 @@ /* H12: Not Connected */ PAD_NC(GPP_H12, NONE), /* H13: PCH M.2 SSD Device Sleep */ - PAD_CFG_GPO(GPP_H13, 0, PLTRST), + PAD_NC(GPP_H13, NONE), /* H14: Not Connected */ PAD_NC(GPP_H14, NONE), /* H15: DDPB Control Clock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8 Gerrit-Change-Number: 86186 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct HDA Subsystem ID
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86212?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/mtl: Correct HDA Subsystem ID ...................................................................... mb/starlabs/starbook/mtl: Correct HDA Subsystem ID This value used was just wrong; set the correct one that matches the verb table. Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/mtl/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index 3181865..956f9c5 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -36,5 +36,5 @@ if (get_uint_option("wireless", 1) == 0) mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8); - mupd->FspmConfig.PchHdaSubSystemIds = 0x14f1035e; + mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098 Gerrit-Change-Number: 86212 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Explicitly set Dq Pins Interleaved
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86211?usp=email ) Change subject: mb/starlabs/*: Explicitly set Dq Pins Interleaved ...................................................................... Patch Set 5: (2 comments) Patchset: PS4: > also appears to need a manual rebase Done Commit Message: https://review.coreboot.org/c/coreboot/+/86211/comment/c3511e55_2347c6af?us… : PS4, Line 10: have one. > line break :) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1aeb8eedf1f57a17e2fe8789379a55ebc9ab1b8c Gerrit-Change-Number: 86211 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Jan 2025 08:46:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/*: Explicitly set Dq Pins Interleaved
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86211?usp=email to look at the new patch set (#5). Change subject: mb/starlabs/*: Explicitly set Dq Pins Interleaved ...................................................................... mb/starlabs/*: Explicitly set Dq Pins Interleaved Explicitly set Dq Pins Interleaved in romstage; enable it for boards with multiple memory controllers and disable it for boards that only have one. Change-Id: I1aeb8eedf1f57a17e2fe8789379a55ebc9ab1b8c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c M src/mainboard/starlabs/starbook/variants/adl/romstage.c M src/mainboard/starlabs/starbook/variants/adl_n/romstage.c M src/mainboard/starlabs/starbook/variants/mtl/romstage.c M src/mainboard/starlabs/starbook/variants/rpl/romstage.c M src/mainboard/starlabs/starbook/variants/tgl/romstage.c M src/mainboard/starlabs/starfighter/variants/rpl/romstage.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c 8 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/86211/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1aeb8eedf1f57a17e2fe8789379a55ebc9ab1b8c Gerrit-Change-Number: 86211 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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coreboot-gerrit January 2025