coreboot-gerrit January 2025

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[L] Change in coreboot[main]: mb/hp: Add Pro 3400
by Angel Pons (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Václav Straka. Angel Pons has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85825?usp=email ) Change subject: mb/hp: Add Pro 3400 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85825/comment/e11073d6_fe483e2f?us… : PS1, Line 11: As a side effect fixed 3500's USB. (broken since 81878) I'm basing this off https://doc.coreboot.org/contributing/gerrit_guidelines.html#recommendation… > Each patch should be kept to one logical change, which should be described in the title of the patch. File src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85825/comment/7490d766_440d4521?us… : PS1, Line 25: device ref pci_bridge off end > I tried finding a workaround for it, but leaving a redundant device in the overlay seems to be the o […] Ah, right, there needs to be a device. I'd say use an EHCI device as dummy, with a comment saying why it's there -- To view, visit https://review.coreboot.org/c/coreboot/+/85825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Gerrit-Change-Number: 85825 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 15:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Václav Straka <venda.straka(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/hp: Add Pro 3400
by Václav Straka (Code Review) 02 Jan '25

02 Jan '25

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[L] Change in coreboot[main]: mb/hp: Add Pro 3400
by Václav Straka (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Angel Pons. Václav Straka has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85825?usp=email ) Change subject: mb/hp: Add Pro 3400 ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85825/comment/d330d012_2f6e5f70?us… : PS1, Line 11: As a side effect fixed 3500's USB. (broken since 81878) > This should belong to a separate commit. I'm not sure what exactly fixed the USB ports. […] USB ports were configured in early_init.c and this change moved it to the devicetree. I just moved the code. I don't think this needs to be another commit since the values are the same just in a different place. I'll fix the reference. File src/mainboard/hp/pro_3x00_series/Kconfig: https://review.coreboot.org/c/coreboot/+/85825/comment/a23801f0_5bcb1c24?us… : PS1, Line 47: default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt" > I think this is the default path That's true. I assumed it isn't and just copied it from hp/snb_ivb_desktops. I will remove it. File src/mainboard/hp/pro_3x00_series/cmos.default: https://review.coreboot.org/c/coreboot/+/85825/comment/34149a65_80d897e1?us… : PS1, Line 6: nmi=Enable > I would disable NMI by default, IIRC the state isn't properly saved/restored so NMI ends up disabled […] Acknowledged File src/mainboard/hp/pro_3x00_series/cmos.layout: https://review.coreboot.org/c/coreboot/+/85825/comment/0a4d3691_f5271523?us… : PS1, Line 26: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 : 960 16 r 0 mrc_scrambler_seed_chk > Unused with native raminit, which is forced on (`select USE_NATIVE_RAMINIT`). Please remove. Acknowledged File src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85825/comment/9dc3fa12_35015754?us… : PS1, Line 24: device ref mei1 off end > Why is this off? If you used me_cleaner or the FDO jumper, the ME stops working properly and vendor […] I copied this from autoport's output, i probably had the FDO jumper on at that time without realizing it. I'll remove this. https://review.coreboot.org/c/coreboot/+/85825/comment/8a519481_1858cea1?us… : PS1, Line 25: device ref pci_bridge off end > This is the default state. This line can be removed. I would remove this but then there would be no devices left on this chip so it wouldn't build. CB:51119 -- To view, visit https://review.coreboot.org/c/coreboot/+/85825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Gerrit-Change-Number: 85825 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 15:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/jasperlake: Remove Cnvi Audio Offload bool
by Sean Rhodes (Code Review) 02 Jan '25

02 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84594?usp=email ) Change subject: soc/intel/jasperlake: Remove Cnvi Audio Offload bool ...................................................................... soc/intel/jasperlake: Remove Cnvi Audio Offload bool This isn't used anywhere, so remove it. Change-Id: Ieb5980929ef35ae129f9e548da7ab71efa2ae7f3 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84594 Reviewed-by: coreboot org <coreboot.org(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/chip.h 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified coreboot org: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 00fac3c..ae0a514 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -227,9 +227,6 @@ /* Enable Pch iSCLK */ bool pch_isclk; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - bool CnviBtAudioOffload; - /* Tcss */ bool TcssXhciEn; bool TcssXdciEn; -- To view, visit https://review.coreboot.org/c/coreboot/+/84594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb5980929ef35ae129f9e548da7ab71efa2ae7f3 Gerrit-Change-Number: 84594 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[L] Change in coreboot[main]: soc/inte/{adl,mtl}: Move ASPM helper functions to common
by Sean Rhodes (Code Review) 02 Jan '25

02 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email ) Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ...................................................................... soc/inte/{adl,mtl}: Move ASPM helper functions to common The ASPM helper functions are the same for all Intel SOCs since Skylake, so move them to common code. Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/Kconfig.common A src/soc/intel/common/block/aspm/Kconfig A src/soc/intel/common/block/aspm/Makefile.mk A src/soc/intel/common/block/aspm/aspm.c A src/soc/intel/common/block/include/intelblocks/aspm.h M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/fsp_params.c 9 files changed, 164 insertions(+), 187 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 15f347f..4f374eb 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI @@ -84,6 +85,7 @@ select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_CRASHLOG if MAINBOARD_HAS_CHROMEOS + select HAS_INTEL_CPU_ROOT_PORTS select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8a03b05..cbfd223d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -18,6 +18,7 @@ #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <gpio.h> +#include <intelblocks/aspm.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> @@ -466,123 +467,6 @@ return config; } -/* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * |-------------------|--------------------------|-----------|-----------| - * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | - * | | PchPcieRpPcieSpeedGen1 | | | - * | | PchPcieRpPcieSpeedGen2 | | | - * | | PchPcieRpPcieSpeedGen3 | | | - * | | PchPcieRpPcieSpeedGen4 | | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int adl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int adl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static unsigned int adl_pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) -{ - /* Use auto unless overwritten */ - if (!pcie_speed_control) - return UPD_INDEX(SPEED_AUTO); - - return UPD_INDEX(pcie_speed_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = - get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->PcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->PcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); - s_cfg->PcieRpPcieSpeed[index] = - adl_pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); -} - -/* - * Starting with Alder Lake, UPDs for Clock Power Management were - * introduced for the CPU root ports. - * - * CpuPcieClockGating: - * Disabled - * Enabled [Default] - * - * CpuPciePowerGating - * Disabled - * Enabled [Default] - * - */ -static void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; - s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; - s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; - s_cfg->CpuPcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->CpuPcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); -} - /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL SKU's */ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_config *config) diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 7ce93d4..7cd5743 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -151,6 +151,11 @@ This will result in a BERT table being populated containing a PMC crashlog record on every boot. +config HAS_INTEL_CPU_ROOT_PORTS + def_bool n + help + Enables helper functions for CPU root ports alongside PCH root ports. + config SOC_INTEL_IOE_DIE_SUPPORT def_bool n help diff --git a/src/soc/intel/common/block/aspm/Kconfig b/src/soc/intel/common/block/aspm/Kconfig new file mode 100644 index 0000000..bab1357 --- /dev/null +++ b/src/soc/intel/common/block/aspm/Kconfig @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_BLOCK_ASPM + bool + help + Intel Processor common ASPM support diff --git a/src/soc/intel/common/block/aspm/Makefile.mk b/src/soc/intel/common/block/aspm/Makefile.mk new file mode 100644 index 0000000..fe6c71d --- /dev/null +++ b/src/soc/intel/common/block/aspm/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ASPM) += aspm.c diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c new file mode 100644 index 0000000..afdf3f6 --- /dev/null +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <intelblocks/aspm.h> +#include <intelblocks/pcie_rp.h> +#include <option.h> +#include <soc/soc_chip.h> +#include <soc/pcie.h> + +/* + * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base + * Specification 1.1. The UPDs and their default values are consistent + * from Skylake through Meteor Lake. However, the default for CPU ports + * differs from PCH ports. Use auto and maximum unless overwritten + * to make the behaviour consistent. + * + * +-------------------+--------------------------+-----------+-----------+ + * | Setting | Option | PCH Ports | CPU Ports | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpEnableCpm | Disabled | [Default] | [Default] | + * | | Enabled | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpAspm | PchPcieAspmDisabled | | | + * | | PchPcieAspmL0s | | | + * | | PchPcieAspmL1 | | | + * | | PchPcieAspmL0sL1 | | [Default] | + * | | PchPcieAspmAutoConfig | [Default] | | + * | | PchPcieAspmMax | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpL1Substates | Disabled | | | + * | | PchPcieL1SubstatesL1_1 | | | + * | | PchPcieL1SubstatesL1_1_2 | | [Default] | + * | | PchPcieL1SubstatesMax | [Default] | | + * |-------------------|--------------------------|-----------|-----------| + * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | + * | | PchPcieRpPcieSpeedGen1 | | | + * | | PchPcieRpPcieSpeedGen2 | | | + * | | PchPcieRpPcieSpeedGen3 | | | + * | | PchPcieRpPcieSpeedGen4 | | | + * +-------------------+--------------------------+-----------+-----------+ + */ + +static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(ASPM_DISABLE); + + /* Use auto unless overwritten */ + if (!aspm_control) + return UPD_INDEX(ASPM_AUTO); + + return UPD_INDEX(aspm_control); +} + +static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Don't enable UPD if Kconfig not set */ + if (!CONFIG(PCIEXP_L1_SUB_STATE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* L1 Substate should be disabled in compliance mode */ + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Use maximum unless overwritten */ + if (!l1_substates_control) + return UPD_INDEX(L1_SS_L1_2); + + return UPD_INDEX(l1_substates_control); +} + +static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) +{ + /* Use auto unless overwritten */ + if (!pcie_speed_control) + return UPD_INDEX(SPEED_AUTO); + + return UPD_INDEX(pcie_speed_control); +} + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + s_cfg->PcieRpEnableCpm[index] = + get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->PcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->PcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); + s_cfg->PcieRpPcieSpeed[index] = + pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); +} + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +/* + * Starting with Alder Lake, UPDs for Clock Power Management were + * introduced for the CPU root ports. + * + * CpuPcieClockGating: + * Disabled + * Enabled [Default] + * + * CpuPciePowerGating + * Disabled + * Enabled [Default] + * + */ +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; + s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; + s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; + s_cfg->CpuPcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->CpuPcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); +} + +#endif // CONFIG(HAS_INTEL_CPU_ROOT_PORTS) diff --git a/src/soc/intel/common/block/include/intelblocks/aspm.h b/src/soc/intel/common/block/include/intelblocks/aspm.h new file mode 100644 index 0000000..297e128 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/aspm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_ASPM_H +#define SOC_INTEL_COMMON_BLOCK_ASPM_H + +#include <intelblocks/pcie_rp.h> + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); +#endif + +#endif /* SOC_INTEL_COMMON_BLOCK_ASPM_H */ diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 73d68df..bc0183d 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -54,6 +54,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 3b4fe46..f3fec48 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -16,6 +16,7 @@ #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <option.h> +#include <intelblocks/aspm.h> #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> @@ -264,76 +265,6 @@ } /* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int mtl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int mtl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->PcieRpAspm[index] = mtl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm); - s_cfg->PcieRpL1Substates[index] = mtl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); -} - -/* * ME End of Post configuration * 0 - Disable EOP. * 1 - Send in PEI (Applicable for FSP in API mode) -- To view, visit https://review.coreboot.org/c/coreboot/+/83679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Gerrit-Change-Number: 83679 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/amd/nova: Add Nova Card common driver
by Ana Carolina Cabral (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Felix Held. Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84776?usp=email ) Change subject: drivers/amd/nova: Add Nova Card common driver ...................................................................... Patch Set 8: (5 comments) File Makefile.mk: https://review.coreboot.org/c/coreboot/+/84776/comment/6d956734_be44a5c4?us… : PS7, Line 121: subdirs-y += src/mainboard/$(MAINBOARDDIR) $(wildcard src/mainboard/*/common) > probably no longer needed after the code was moved to the driver directory Done File src/drivers/amd/nova/Kconfig: https://review.coreboot.org/c/coreboot/+/84776/comment/9a60e35d_dbe5a3af?us… : PS5, Line 4: def_bool n > the AMD mainboard with a slot for a nova card should select this kconfig directly and not via the de […] Acknowledged File src/drivers/amd/nova/chip.h: https://review.coreboot.org/c/coreboot/+/84776/comment/136ee753_3ae6cde6?us… : PS7, Line 9: #define NOVA_CARD_EEPROM_CONNECTOR_TYPE_OFFSET 2 > i'd move this define into the c file that uses this, since it's not needed outside of that c file Done https://review.coreboot.org/c/coreboot/+/84776/comment/1792a405_11a63467?us… : PS7, Line 10: #define NOVA_CARD_EEPROM_I2C_BUS 2 : #define NOVA_CARD_EEPROM_I2C_ADDRESS 0x55 > those two are mainboard-dependend. […] I put it there as a "default" value, but each board can use a different setup when calling the function. Is it better to move this to each mb/port_descriptors.c file? File src/drivers/amd/nova/nova_card.c: https://review.coreboot.org/c/coreboot/+/84776/comment/0b5b1f26_767fb0ec?us… : PS7, Line 9: #include <soc/amd/phoenix/chip_opensil.h> > i'd like to avoid soc-specific code in a common driver I can move ddi_connector_type enum to nova/chip.h, since they are only being used in this function, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 8 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jan 2025 14:54:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anand Vaikar <a.vaikar2021(a)gmail.com> Comment-In-Reply-To: Ana Carolina Cabral Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: mb/hp: Add Pro 3400
by Václav Straka (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Václav Straka. Václav Straka has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85825?usp=email ) Change subject: mb/hp: Add Pro 3400 ...................................................................... mb/hp: Add Pro 3400 Based on autoport and HP Pro 3500. As part of this change renamed 3500 to 3x00 and added this as it's variant. As a side effect fixed 3500's USB. (broken since CB:81878) Add CMOS option table. It's an almost identical board to the 3500 but has a smaller flash. Other differences between boards were identified by autoport. They may or may not important but were included anyway. Tested on HP Pro 3400, behaves exactly as 3500 described in the docs. Changes were not significant enough to require retesting on 3500. Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Signed-off-by: Vesek <venda.straka(a)gmail.com> --- D Documentation/mainboard/hp/pro_3500_series.md A Documentation/mainboard/hp/pro_3x00_series.md R Documentation/mainboard/hp/pro_3x00_series_flash.avif R Documentation/mainboard/hp/pro_3x00_series_jumper.avif M Documentation/mainboard/index.md D src/mainboard/hp/pro_3500_series/Kconfig A src/mainboard/hp/pro_3x00_series/Kconfig R src/mainboard/hp/pro_3x00_series/Kconfig.name R src/mainboard/hp/pro_3x00_series/Makefile.mk R src/mainboard/hp/pro_3x00_series/acpi/ec.asl R src/mainboard/hp/pro_3x00_series/acpi/platform.asl R src/mainboard/hp/pro_3x00_series/acpi/superio.asl R src/mainboard/hp/pro_3x00_series/acpi_tables.c A src/mainboard/hp/pro_3x00_series/board_info.txt A src/mainboard/hp/pro_3x00_series/cmos.default A src/mainboard/hp/pro_3x00_series/cmos.layout R src/mainboard/hp/pro_3x00_series/common_defines.h R src/mainboard/hp/pro_3x00_series/devicetree.cb R src/mainboard/hp/pro_3x00_series/dsdt.asl R src/mainboard/hp/pro_3x00_series/early_init.c R src/mainboard/hp/pro_3x00_series/gma-mainboard.ads R src/mainboard/hp/pro_3x00_series/hda_verb.c R src/mainboard/hp/pro_3x00_series/led.c R src/mainboard/hp/pro_3x00_series/led.h R src/mainboard/hp/pro_3x00_series/mainboard.c R src/mainboard/hp/pro_3x00_series/smihandler.c C src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/board_info.txt A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/data.vbt A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/gpio.c A src/mainboard/hp/pro_3x00_series/variants/pro_3400_series/overridetree.cb R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/board_info.txt R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/data.vbt R src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/gpio.c A src/mainboard/hp/pro_3x00_series/variants/pro_3500_series/overridetree.cb 34 files changed, 504 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85825/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387 Gerrit-Change-Number: 85825 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com>

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Ana Carolina Cabral (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Anand Vaikar, Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Ana Carolina Cabral has posted comments on this change by Anand Vaikar. ( https://review.coreboot.org/c/coreboot/+/85749?usp=email ) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... Patch Set 7: (2 comments) File src/mainboard/amd/crater/Kconfig: https://review.coreboot.org/c/coreboot/+/85749/comment/785fe8fe_b114ecd0?us… : PS7, Line 49: EC_birmanplus_sig Birmanplus file https://review.coreboot.org/c/coreboot/+/85749/comment/7cc32bac_2ff4835a?us… : PS7, Line 78: This is a birmanplus specific override of soc/amd/(phoenix | glinda)/Kconfig Birmanplus file -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 7 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jan 2025 14:31:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Nicholas Chin (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: (1 comment) File src/drivers/asmedia/asm1061.c: PS5: Looks like this is changed just enough that Git/Gerrit doesn't detect the rename. Seems like the similarity threshold is 50%. -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 14:22:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Nicholas Chin (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: (1 comment) File src/drivers/asmedia/asm1061.c: https://review.coreboot.org/c/coreboot/+/85816/comment/1ea2d8ec_dbe74f02?us… : PS5, Line 40: 0x0611, /* ASM1061 SATA IDE Controller */ > Does the device ID change when switching to SATA mode? Yes, the device ID changes from 0x611 to 0x0612 after the subclass code register is written. -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 14:20:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit January 2025