coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Felix Held (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Ana Carolina Cabral, Paul Menzel. Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86084?usp=email ) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... Patch Set 11: (1 comment) File src/mainboard/amd/birman_plus/ec.c: https://review.coreboot.org/c/coreboot/+/86084/comment/6eed47c5_13bdfeaf?us… : PS11, Line 35: one tab too much -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 11 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 19:27:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update PCIe Slot configurations
by Felix Held (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Ana Carolina Cabral. Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85493?usp=email ) Change subject: mb/amd/birman_plus: Update PCIe Slot configurations ...................................................................... Patch Set 21: (1 comment) File src/mainboard/amd/birman_plus/port_descriptors_glinda.c: PS21: do the function numbers match the ones in the uefi reference implementation? older platforms have some specific requirements about the function numbers in relation to the lane numbers; i'm not sure if that still applies to the current silicon. another thing that should be done, possibly in a follow-up, is to update the devicetree to enable the device functions that are set up by these descriptors -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 21 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 19:25:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Jérémy Compostella (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Jérémy Compostella has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 19:04:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Jérémy Compostella (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Jérémy Compostella has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: I see than tone File src/soc/intel/common/block/cse/telemetry.c: https://review.coreboot.org/c/coreboot/+/86215/comment/3c5e4cdc_1a4012d0?us… : PS2, Line 7: s64 > Why is process_cse_telemetry_data() dealing with signed for timestamps? I see that tons of function around the area of the timestamps are dealing with signed so this is weird but out of the scope of this CL. Marking resolved. -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 19:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Jérémy Compostella (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Jérémy Compostella has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: Why is process_cse_telemetry_data() dealing with signed for timestamps. File src/soc/intel/common/block/cse/telemetry.c: https://review.coreboot.org/c/coreboot/+/86215/comment/0bdf3f25_9e9be641?us… : PS2, Line 7: s64 > shouldn't it be u64 ? Why is process_cse_telemetry_data() dealing with signed for timestamps? -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 19:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Jérémy Compostella (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Jérémy Compostella has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/telemetry.c: https://review.coreboot.org/c/coreboot/+/86215/comment/436337ae_d858ac4c?us… : PS2, Line 7: s64 shouldn't it be u64 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 18:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Disable separate romstage for emulation builds
by David Hendricks (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Angel Pons, Arthur Heymans, Simon Glass. David Hendricks has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/79079?usp=email ) Change subject: Disable separate romstage for emulation builds ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: FYI - CB:63419 is an alternative approach that might be preferable. -- To view, visit https://review.coreboot.org/c/coreboot/+/79079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4fa8322dba9b5a46c5a73489cb396199621e068 Gerrit-Change-Number: 79079 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Jan 2025 18:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/crossgcc: Add missing printf variable
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86148?usp=email ) Change subject: util/crossgcc: Add missing printf variable ...................................................................... util/crossgcc: Add missing printf variable Add the printing of the missing libstdcxx path in the warning string when the path check fails. Also resolve the use of the variable in the conditional statement by surrounding it with quotes. BUG=None TEST=Build with invalid libstdcxx path Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86148 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 2d112eb..2ad98b8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -856,9 +856,9 @@ } build_LIBSTDCXX() { - if [ ! -e ${LIBSTDCXX_INCLUDE_PATH} ]; then + if [ ! -e "${LIBSTDCXX_INCLUDE_PATH}" ]; then touch .failed - printf "libstdcxx include path \"%s\" does not exist" + printf "libstdcxx include path \"%s\" does not exist" "${LIBSTDCXX_INCLUDE_PATH}" return fi configure_GCC \ -- To view, visit https://review.coreboot.org/c/coreboot/+/86148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Gerrit-Change-Number: 86148 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Angel Pons (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Alicja Michalska, Arthur Heymans. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 4: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/86131/comment/d06cdc64_7020d962?us… : PS4, Line 1015: default y > is it intended that the default is changed for all non-x86 arcitectures? I don't think it is -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 4 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 29 Jan 2025 18:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: nb/intel/i440bx: Drop self-specific debugging macros
by David Hendricks (Code Review) 29 Jan '25

29 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78786?usp=email ) Change subject: nb/intel/i440bx: Drop self-specific debugging macros ...................................................................... nb/intel/i440bx: Drop self-specific debugging macros Replace PRINT_DEBUG() macro with printram() from device/dram/common.h for raminit debug messages. Define a static dummy dump_pci_device() if CONFIG(DEBUG_RAM_SETUP) is disabled. This allows removing the DUMPNORTH() macro. dump_spd_registers() will be cleaned up separately. TEST=Timeless binary remains unchanged. Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78786 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 27 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 54c1b36..f82d54c 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -3,6 +3,7 @@ #include <spd.h> #include <delay.h> #include <stdint.h> +#include <device/dram/common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -17,13 +18,9 @@ * Macros and definitions */ -/* Debugging macros. */ -#if CONFIG(DEBUG_RAM_SETUP) -#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define DUMPNORTH() dump_pci_device(NB) -#else -#define PRINT_DEBUG(x...) -#define DUMPNORTH() +/* Debugging stub */ +#if !CONFIG(DEBUG_RAM_SETUP) +static void dump_pci_device(unsigned int dev) {} #endif /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ @@ -631,7 +628,7 @@ continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; - PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); + printram(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); } pci_write_config8(NB, DRAMC, reg); @@ -645,8 +642,8 @@ { int i, max; - PRINT_DEBUG("Northbridge %s SDRAM init:\n", "prior to"); - DUMPNORTH(); + printram("Northbridge %s SDRAM init:\n", "prior to"); + dump_pci_device(NB); max = ARRAY_SIZE(register_values); @@ -713,12 +710,12 @@ * modules by setting them to a supported size. */ if (sz.side1 > 128) { - PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", + printram("Side%d was %dMB but only 128MB will be used.\n", 1, sz.side1); sz.side1 = 128; if (sz.side2 > 128) { - PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", + printram("Side%d was %dMB but only 128MB will be used.\n", 2, sz.side2); sz.side2 = 128; } @@ -760,7 +757,7 @@ } else if (value == SPD_MEMORY_TYPE_SDRAM) { sd = 1; } - PRINT_DEBUG("Found DIMM in slot %d\n", i); + printram("Found DIMM in slot %d\n", i); if (edo && sd) { die_with_post_code(POSTCODE_RAM_FAILURE, @@ -803,12 +800,12 @@ */ value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES); - PRINT_DEBUG("DIMM is "); + printram("DIMM is "); if ((value & MODULE_REGISTERED) == 0) { regsd = 0; - PRINT_DEBUG("not "); + printram("not "); } - PRINT_DEBUG("registered\n"); + printram("registered\n"); /* Calculate page size in bits. */ value = ((1 << col) * width); @@ -839,7 +836,7 @@ /* Page sizes larger than supported are * set to 8KB to use module partially. */ - PRINT_DEBUG("Page size forced to 8KB.\n"); + printram("Page size forced to 8KB.\n"); dra = 0x2; /* 8KB */ } else { dra = -1; @@ -859,7 +856,7 @@ dra = 0x0a; /* 8KB */ } else if (dra >= 16) { /* Ditto */ - PRINT_DEBUG("Page size forced to 8KB.\n"); + printram("Page size forced to 8KB.\n"); dra = 0x0a; /* 8KB */ } else { dra = -1; @@ -918,15 +915,15 @@ /* Set paging policy register. */ pci_write_config8(NB, PGPOL + 1, bpr); - PRINT_DEBUG("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr); + printram("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr); /* Set DRAM row page size register. */ pci_write_config16(NB, RPS, rps); - PRINT_DEBUG("RPS has been set to 0x%04x\n", rps); + printram("RPS has been set to 0x%04x\n", rps); /* ### ECC */ pci_write_config8(NB, NBXCFG + 3, nbxecc); - PRINT_DEBUG("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc); + printram("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc); /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */ @@ -942,7 +939,7 @@ value = pci_read_config8(NB, DRAMC) & 0xe7; value |= i; pci_write_config8(NB, DRAMC, value); - PRINT_DEBUG("%s has been set to 0x%02x\n", "DRAMC", value); + printram("%s has been set to 0x%02x\n", "DRAMC", value); } static void sdram_enable(void) @@ -953,40 +950,40 @@ udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ - PRINT_DEBUG("RAM Enable %d: %s\n", 1, "Apply NOP"); + printram("RAM Enable %d: %s\n", 1, "Apply NOP"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 2, "Precharge all"); + printram("RAM Enable %d: %s\n", 2, "Precharge all"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 3, "CBR"); + printram("RAM Enable %d: %s\n", 3, "CBR"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 4, "Mode register set"); + printram("RAM Enable %d: %s\n", 4, "Mode register set"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 5, "Normal operation"); + printram("RAM Enable %d: %s\n", 5, "Normal operation"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 6, "Enable refresh"); + printram("RAM Enable %d: %s\n", 6, "Enable refresh"); pci_write_config8(NB, PMCR, 0x10); spd_enable_refresh(); udelay(1); - PRINT_DEBUG("Northbridge %s SDRAM init:\n", "following"); - DUMPNORTH(); + printram("Northbridge %s SDRAM init:\n", "following"); + dump_pci_device(NB); } /* Implemented under mainboard. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec Gerrit-Change-Number: 78786 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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coreboot-gerrit January 2025