coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/baytrail: Add microcode for '06-37-08' SOCs
by Felix Singer (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Máté Kukri. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/86217?usp=email ) Change subject: soc/intel/baytrail: Add microcode for '06-37-08' SOCs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0 Gerrit-Change-Number: 86217 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 17:22:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 5: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/fb5b1fbc_cb2a6c8b?us… : PS2, Line 77: {7, 34, 20, -1} > Hmm, supposedly the ASM1061 worked in the original P8Z77-V port Wow, all these went under my nose unnoticed! And to think that I should have a bit of an idea what PP and OD means individually, and Bill's vendor log (which I saved) did show that PP/OD register set as 0x8c. I just pushed an update with the fix Let's see how it works for Bill. (To think of it, before this update PCIEX16_3 at 4x probably would not work even with straps set, if Bill were to try.) -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 17:08:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region
by Máté Kukri (Code Review) 29 Jan '25

29 Jan '25

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86219?usp=email ) Change subject: mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region ...................................................................... mb/bostentech/gbyt4: Increase default CBFS size to cover BIOS region There is no reason to default to a 1MB CBFS when the descriptor gives us 5MB to work with. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d --- M src/mainboard/bostentech/gbyt4/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/86219/1 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index 3027273..acfa313 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -12,6 +12,9 @@ select SOC_INTEL_BAYTRAIL select SUPERIO_ITE_IT8728F +config CBFS_SIZE + default 0x500000 + config MAINBOARD_DIR default "bostentech/gbyt4" -- To view, visit https://review.coreboot.org/c/coreboot/+/86219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d Gerrit-Change-Number: 86219 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz>

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[XS] Change in coreboot[main]: mb/bostentech/gbyt4: Add VBT
by Máté Kukri (Code Review) 29 Jan '25

29 Jan '25

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86218?usp=email ) Change subject: mb/bostentech/gbyt4: Add VBT ...................................................................... mb/bostentech/gbyt4: Add VBT This is useful when booted with the (not yet mainline) libgfxinit for Bay Trail. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170 --- M src/mainboard/bostentech/gbyt4/Kconfig A src/mainboard/bostentech/gbyt4/data.vbt 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/86218/1 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index 51e9209..3027273 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -4,11 +4,12 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_BAYTRAIL select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/bostentech/gbyt4/data.vbt b/src/mainboard/bostentech/gbyt4/data.vbt new file mode 100644 index 0000000..ed02d64 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/86218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170 Gerrit-Change-Number: 86218 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz>

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[XS] Change in coreboot[main]: soc/intel/baytrail: Add microcode for '06-37-08' SOCs
by Máté Kukri (Code Review) 29 Jan '25

29 Jan '25

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86217?usp=email ) Change subject: soc/intel/baytrail: Add microcode for '06-37-08' SOCs ...................................................................... soc/intel/baytrail: Add microcode for '06-37-08' SOCs Previously only the '06-37-03' and '06-37-09' microcode files were provided but '06-37-08' was missing. Linux on my '06-37-08' SOC was segfaulting in various unpredictable ways without this patch. Signed-off-by: Mate Kukri <km(a)mkukri.xyz> Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0 --- M src/soc/intel/baytrail/Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86217/1 diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 281175c..bef8c0e 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -65,6 +65,7 @@ postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \ + 3rdparty/intel-microcode/intel-ucode/06-37-08 \ 3rdparty/intel-microcode/intel-ucode/06-37-09 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include -- To view, visit https://review.coreboot.org/c/coreboot/+/86217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0 Gerrit-Change-Number: 86217 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Subrata Banik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Subrata Banik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 16:46:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/*: Correct config for SATA DEVSLP GPIO
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86186?usp=email ) Change subject: mb/starlabs/*: Correct config for SATA DEVSLP GPIO ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8 Gerrit-Change-Number: 86186 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 29 Jan 2025 16:38:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/asus/p8x7x-series: Hide nonexistent IVB devices
by Keith Hui (Code Review) 29 Jan '25

29 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86185?usp=email to look at the new patch set (#2). Change subject: mb/asus/p8x7x-series: Hide nonexistent IVB devices ...................................................................... mb/asus/p8x7x-series: Hide nonexistent IVB devices Hide peg12, dev4, and peg60 devices to squelch leftover devices warning seen with p8z77-m, p8z77-v and p8z77-v_le_plus: [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:00:01.1 [WARN ] PCI: 00:00:01.2 [WARN ] PCI: 00:00:04.0 [WARN ] PCI: 00:00:06.0 [WARN ] PCI: Check your devicetree.cb. No board in this family can do the 8/4/4 PCIe lane split to require the peg12 bridge, or implemented dev4 at all. Only p8c_ws wired up the 4 extra Xeon PCIe lanes peg60 is supposed to cover, and its overridetree already enables it. Therefore, be proactive and hide these from the rest of the family. Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/86185/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f Gerrit-Change-Number: 86185 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Angel Pons, Bill XIE, Keith Hui. Hello Bill XIE, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85413?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... mb/asus/p8z77-v: Attempt to correctly route PCIe lanes Bill Xie documented in his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. Another one needs to be added later to enable users to allocate all lanes to PCIEX16_3 and make it x4. 3. Add code to bootblock to check the PCHSTRP9 soft strap and whether (1) is true. There is a sanity check to warn of a PCIe configuration that is not valid on this board. 4. Based on (1) and (2), program SIO GPIO5 as appropriate. Remove all GPIO5 settings from devicetree so this code has full control. Changing PCIEX16_3 from x1 to x4 (and vice versa) requires changing PCHSTRP9 in the SPI flash descriptor. How coreboot can manage this is TBD. This is based on boardview only, and is untested because I have no hardware. Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb 5 files changed, 119 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/common/block/pci: Ignore disabled bridges
by Patrick Rudolph (Code Review) 29 Jan '25

29 Jan '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86216?usp=email ) Change subject: soc/amd/common/block/pci: Ignore disabled bridges ...................................................................... soc/amd/common/block/pci: Ignore disabled bridges To avoid PCI resource conflicts always assert and ignore when an internal dummy PCIe bridge is marked as disabled. This allows to boot on AMD/birman+ to UEFI shell. The PCI bridge device will get properly configured and as the scan for sub-ordinate devices is disabled, will not delay boot and will never claim any resources. Change-Id: Ia97098c860aa6cd6b0b59aa7b1c6f7c239e41983 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86216/1 diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 0f983d0..9cc4c45 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -47,6 +47,28 @@ acpigen_pop_len(); /* Scope */ } +struct device_operations amd_pcie_disabled_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, +}; + +static void pcie_internal_gpp_enable(struct device *dev) +{ + assert(dev->enabled); + if (!dev->enabled) { + /* + * Cannot hide PPB devices! Must keep them enabled to + * make sure PCI enumeration runs and avoids resource conflicts. + */ + dev->enabled = true; + dev->hidden = true; + dev->ops = &amd_pcie_disabled_gpp_ops; + } +} + /* Latency tolerance reporting, max snoop/non-snoop latency value 1.049ms */ #define PCIE_LTR_MAX_LATENCY_1049US 0x1001 @@ -62,6 +84,7 @@ }; struct device_operations amd_internal_pcie_gpp_ops = { + .enable = pcie_internal_gpp_enable, .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/86216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia97098c860aa6cd6b0b59aa7b1c6f7c239e41983 Gerrit-Change-Number: 86216 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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coreboot-gerrit January 2025