coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Work around FSP bug
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Patrick Rudolph, Paul Menzel. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85789?usp=email ) Change subject: cpu/x86/64bit/mode_switch: Work around FSP bug ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/cpu/x86/64bit/mode_switch.S: https://review.coreboot.org/c/coreboot/+/85789/comment/125fd132_05474c92?us… : PS3, Line 50: lidt -16(%ebp) > should it be lidt (%ebp)? (per ln22-27) Sorry, my bad, it is the zero IDT instead of the back up IDT, no opens. LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 06 Jan 2025 04:49:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85841?usp=email ) Change subject: soc/mediatek/mt8196: Add clk_buf drivers ...................................................................... Patch Set 1: (33 comments) File src/soc/mediatek/mt8196/clkbuf_ctl.c: https://review.coreboot.org/c/coreboot/+/85841/comment/faa5d937_81451b44?us… : PS1, Line 9: Remove 1 tab. https://review.coreboot.org/c/coreboot/+/85841/comment/babf3769_3f5b5932?us… : PS1, Line 15: * space https://review.coreboot.org/c/coreboot/+/85841/comment/909c5380_f53be9fd?us… : PS1, Line 17: #define XO_IMPEDANCE_SHIFT 3 Add a blank line below. https://review.coreboot.org/c/coreboot/+/85841/comment/3bfe5c77_93c73f70?us… : PS1, Line 20: XO_MODE_SHIFT Remove and use `XO_EN_MODE_SHIFT` defined above. I assume they are the same thing. https://review.coreboot.org/c/coreboot/+/85841/comment/7ae7ef64_cfbb7eb5?us… : PS1, Line 22: #define clk_buf_enable_xo(xo_id) \ : mt6685_write_field(ox[(xo_id)].reg, \ : XO_RC_MODE, \ : XO_EN_MODE_MASK, \ : XO_MODE_SHIFT) : : #define clk_buf_disable_xo(xo_id) \ : mt6685_write_field(ox[(xo_id)].reg, \ : XO_DISABLE_MODE, \ : XO_EN_MODE_MASK, \ : XO_MODE_SHIFT) : : #define clk_buf_impedance_config(xo_id) \ : mt6685_write_field(ox[(xo_id)].reg, \ : ox[(xo_id)].impedance, \ : XO_IMPEDANCE_MASK, \ : XO_IMPEDANCE_SHIFT) : : #define clk_buf_driving_config(xo_id) \ : mt6685_write_field(ox[(xo_id)].reg, \ : ox[(xo_id)].driving, \ : XO_DRIVING_MASK, \ : XO_DRIVING_SHIFT) Change to static inline functions. https://review.coreboot.org/c/coreboot/+/85841/comment/ef303452_f5dd5900?us… : PS1, Line 48: /* SPMI master/slave, might change in the future */ : #define CLKBUF_SPMI_MASTER SPMI_MASTER_1 : #define CLKBUF_SPMI_SLAVE SPMI_SLAVE_9 Remove if unused. https://review.coreboot.org/c/coreboot/+/85841/comment/8fa75995_1c8bd167?us… : PS1, Line 74: struct ox_cfg ox[] = { static const https://review.coreboot.org/c/coreboot/+/85841/comment/fe0c57b1_0c60d12e?us… : PS1, Line 148: impedance = 0, : .driving = 0, : .voter_mask = { : .low_byte = 0x0, : .high_byte = 0x0, : }, : For `CLOCK_BUFFER_DISABLE`, fields `impedance`, `driving` and `voter_mask` are NOT used. Let's skip the initialization for them. https://review.coreboot.org/c/coreboot/+/85841/comment/17787338_b3b88ae9?us… : PS1, Line 207: unsigned int Should this be u16? https://review.coreboot.org/c/coreboot/+/85841/comment/9a6b1e1e_ebf0256c?us… : PS1, Line 209: unsigned int out = 0; : unsigned char tmp = 0; : : tmp = mt6685_read8(MT6685_PMRC_CON0); : out = tmp; : tmp = mt6685_read8(MT6685_PMRC_CON1); : out |= tmp << 8; Use `mt6685_read_low_high`, which I suggested in another comment. https://review.coreboot.org/c/coreboot/+/85841/comment/f9786ea6_31c3d1d1?us… : PS1, Line 222: u8 `int`. Please fix all `u8 i` in this file. https://review.coreboot.org/c/coreboot/+/85841/comment/380ddc02_dae31932?us… : PS1, Line 228: \n Print the newline at the end of the string (NOT before). You'll need to add a newline for the string in line #224. https://review.coreboot.org/c/coreboot/+/85841/comment/27ccb7fa_0550a087?us… : PS1, Line 260: clk_buf_dump_clkbuf_log dump_clkbuf_log https://review.coreboot.org/c/coreboot/+/85841/comment/c74c9641_4a016e97?us… : PS1, Line 269: Add ``` _Static_assert(MT6685_XO_BUF_CTL0_L + 2 * (XO_NUMBER - 1) == MT6685_XO_BUF_CTL12_L, "Wrong reg for MT6685_XO_BUF_CTL12_L"); _Static_assert(MT6685_XO_BUF_CTL0_H + 2 * (XO_NUMBER - 1) == MT6685_XO_BUF_CTL12_H, "Wrong reg for MT6685_XO_BUF_CTL12_H"); ``` https://review.coreboot.org/c/coreboot/+/85841/comment/bcfc35de_0034a599?us… : PS1, Line 271: xo_buf_cw[i] = mt6685_read8(MT6685_DCXO_EXTBUF1_CW0 + i); : val = mt6685_read8(MT6685_XO_BUF_CTL0_L + (2 * i)); : xo_buf_vote[i] = val; : : val = mt6685_read8(MT6685_XO_BUF_CTL0_H + (2 * i)); : xo_buf_vote[i] |= (val << 8); Add a helper function for reading L and H regs. ``` static u16 mt6685_read_low_high(u32 low_reg, u32 high_reg) { u16 data = mt6685_read8(low_reg); data |= mt6685_read8(high_reg) << 8; return data; } ``` https://review.coreboot.org/c/coreboot/+/85841/comment/220c4646_b68b9848?us… : PS1, Line 283: RG_XO_DIG26M_DIV2_MASK, align https://review.coreboot.org/c/coreboot/+/85841/comment/743b0a51_120ceb19?us… : PS1, Line 286: 0x79A Print `%#X` for `MT6685_DCXO_EXTBUF1_CW0`. https://review.coreboot.org/c/coreboot/+/85841/comment/71ddb3d0_e77f2acf?us… : PS1, Line 286: __func__ We don't need to print the function name so many times. How about adding `[clkbuf]` prefix for these logs? https://review.coreboot.org/c/coreboot/+/85841/comment/298c2cd6_2162bbe6?us… : PS1, Line 291: 0x54C `MT6685_XO_BUF_CTL0_L` https://review.coreboot.org/c/coreboot/+/85841/comment/c0572e55_fb3fb3fb?us… : PS1, Line 333: XO_BBCK1_VOTE_L_ADDR Write `MT6685_XO_BUF_CTL0_L` here to be consistent with `clk_buf_dump_clkbuf_log`. https://review.coreboot.org/c/coreboot/+/85841/comment/795b99d6_577ec7dc?us… : PS1, Line 324: for (i = 0; i < XO_NUMBER; ++i) { : if (ox[i].mode == CLOCK_BUFFER_DISABLE) { : ox[i].voter_mask.low_byte = 0; : ox[i].voter_mask.high_byte = 0; : } : } : : /* 1.4 Write RC voting table */ : for (i = 0; i < XO_NUMBER; i++) { : mt6685_write8(XO_BBCK1_VOTE_L_ADDR + (2 * i), : ox[i].voter_mask.low_byte); : mt6685_write8(XO_BBCK1_VOTE_H_ADDR + (2 * i), : ox[i].voter_mask.high_byte); : } Combine them: ``` for (i ...) { u8 low, high; if (ox[i].mode == CLOCK_BUFFER_DISABLE) { low = 0; high = 0; } else { low = ox[i].voter_mask.low_byte; high = ox[i].voter_mask.high_byte; } mt6685_write8(..., low); mt6685_write8(..., high); } ``` https://review.coreboot.org/c/coreboot/+/85841/comment/5e6716b8_4560067f?us… : PS1, Line 339: t T https://review.coreboot.org/c/coreboot/+/85841/comment/bce1cc5c_ee5c4e72?us… : PS1, Line 355: t T https://review.coreboot.org/c/coreboot/+/85841/comment/347104da_69c19cc1?us… : PS1, Line 380: /* 1.8 RC mode setting Wrong comment format. https://review.coreboot.org/c/coreboot/+/85841/comment/8b6b5442_ed773adb?us… : PS1, Line 385: ( remove https://review.coreboot.org/c/coreboot/+/85841/comment/8dd6a3eb_fb05cde5?us… : PS1, Line 397: mt6685_write8(XO_STATIC_AUXOUT_SEL_ADDR, sel); Should we use `mt6685_write_field` and specify `XO_STATIC_AUXOUT_SEL_MASK` and `_SHIFT`? https://review.coreboot.org/c/coreboot/+/85841/comment/3d733d86_cdd70fd3?us… : PS1, Line 399: tmp = mt6685_read8(XO_STATIC_AUXOUT_L_ADDR); : val = tmp; : : tmp = mt6685_read8(XO_STATIC_AUXOUT_H_ADDR); : val |= tmp << 8; Use `mt6685_read_low_high`. https://review.coreboot.org/c/coreboot/+/85841/comment/286cc195_5ac5e984?us… : PS1, Line 418: d D File src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h: https://review.coreboot.org/c/coreboot/+/85841/comment/70f717b6_a5be9570?us… : PS1, Line 78: * Space. Same for all similar cases below. https://review.coreboot.org/c/coreboot/+/85841/comment/703bad3f_74ea4c2e?us… : PS1, Line 453: CLOCK_BUFFER_HW_CONTROL Add `,` https://review.coreboot.org/c/coreboot/+/85841/comment/1588e3d2_3f7af4c7?us… : PS1, Line 464: CLK_BUF_OUTPUT_IMPEDANCE_7 Add `,` https://review.coreboot.org/c/coreboot/+/85841/comment/84220ba8_090fdfeb?us… : PS1, Line 536: clk_buf_set_default Remove if unused. https://review.coreboot.org/c/coreboot/+/85841/comment/941d3bc5_ac17e1bb?us… : PS1, Line 538: pwrap_interface_init Remove if unused. -- To view, visit https://review.coreboot.org/c/coreboot/+/85841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Gerrit-Change-Number: 85841 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 03:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rauru: Add alc5650 support
by Yang Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85858?usp=email to look at the new patch set (#2). Change subject: mb/google/rauru: Add alc5650 support ...................................................................... mb/google/rauru: Add alc5650 support Configure ALC5650 for hylia to support beep sound in depthcharge. BRANCH=rauru BUG=b:383376419 TEST=Verify devbeep in depthcharge console Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/mainboard.c 4 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/85858/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988 Gerrit-Change-Number: 85858 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Add alc5650 support
by Yang Wu (Code Review) 06 Jan '25

06 Jan '25

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85858?usp=email ) Change subject: mb/google/rauru: Add alc5650 support ...................................................................... mb/google/rauru: Add alc5650 support Configure ALC5650 for hylia to support beep sound in depthcharge. BRANCH=rauru BUG=b:383376419 TEST=Verify devbeep in depthcharge console Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988 Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/mainboard.c 4 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/85858/1 diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index f530396..6a34cb9 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -46,8 +46,14 @@ {GPIO_EN_SPKR.id, ACTIVE_LOW, -1, "speaker reset"}, }; + struct lb_gpio alc5645_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) lb_add_gpios(gpios, smartamp_gpios, ARRAY_SIZE(smartamp_gpios)); + else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) + lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios)); else lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios)); } diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb index 7f6dc59..1705dbe 100644 --- a/src/mainboard/google/rauru/devicetree.cb +++ b/src/mainboard/google/rauru/devicetree.cb @@ -4,6 +4,7 @@ field AUDIO_AMP 28 29 option AMP_NAU8318 0 option AMP_TAS2563 1 + option AMP_ALC5645 2 end end diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index 6191e05..ef7db86 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -20,6 +20,11 @@ #define GPIO_I2SI4_LRCK GPIO(I2SIN1_LRCK) #define GPIO_I2SO4_D0 GPIO(I2SOUT1_DO) +#define GPIO_I2SI6_MCK GPIO(I2SIN0_MCK) +#define GPIO_I2SI6_BCK GPIO(I2SIN0_BCK) +#define GPIO_I2SI6_LRCK GPIO(I2SIN0_LRCK) +#define GPIO_I2SO6_D0 GPIO(I2SOUT0_DO) + void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index a49caf6..c1090e3 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -29,11 +29,29 @@ gpio_set_mode(GPIO_I2SO4_D0, GPIO_FUNC(I2SOUT1_DO, I2SOUT4_DATA0)); } +static void configure_alc5645(void) +{ + write32p(AFE_SE_SECURE_CON1, 0x0); + /* Set up I2S */ + gpio_set_mode(GPIO_I2SI6_MCK, GPIO_FUNC(I2SIN0_MCK, I2S_MCK0)); + gpio_set_mode(GPIO_I2SI6_BCK, GPIO_FUNC(I2SIN0_BCK, I2SIN6_0_BCK)); + gpio_set_mode(GPIO_I2SI6_LRCK, GPIO_FUNC(I2SIN0_LRCK, I2SIN6_0_LRCK)); + gpio_set_mode(GPIO_I2SO6_D0, GPIO_FUNC(I2SOUT0_DO, I2SOUT6_0_DO)); + + /* Init I2C bus timing register for audio codecs */ + mtk_i2c_bus_init(I2C3, I2C_SPEED_STANDARD); +} static void configure_audio(void) { if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) { mtk_i2c_bus_init(I2C3, I2C_SPEED_FAST); configure_i2s(); + printk(BIOS_INFO, "Audio configure TAS2563\n"); + } else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) { + configure_alc5645(); + printk(BIOS_INFO, "Audio configure ALC5645\n"); + } else { + printk(BIOS_INFO, "Audio configure default amps NAU8318\n"); } printk(BIOS_INFO, "%s: done\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/85858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988 Gerrit-Change-Number: 85858 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Determine PCIe init by storage_id
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85828?usp=email ) Change subject: mb/google/rauru: Determine PCIe init by storage_id ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85828/comment/71713349_9ed688b7?us… : PS2, Line 52: return storage_id() == 3; Can we modify `storage_type()` to return `enum storage_type` (by renaming `ufs_type`)? We could use the high bits to differentiate between UFS and NVMe. ``` # Bits [31:28] for base type (e.g. UFS). #define _BASE_TYPE_SHIFT 28 #define _BASE_TYPE_MASK (0xf << _BASE_TYPE_SHIFT) #define _BASE_TYPE(x) ((x & 0xf) << _BASE_TYPE_SHIFT) #define _BASE_TYPE_UFS _BASE_TYPE(0x0) #define _BASE_TYPE_NVME _BASE_TYPE(0x1) enum storage_type { STORAGE_UNKNOWN = 0, STORAGE_UFS_31 = _BASE_TYPE_UFS | 0x310, ... STORAGE_NVME = _BASE_TYPE_NVME, }; enum storage_type storage_type(void) { uint32_t index = storage_id(); switch (index) ... } static inline storage_is_nvme(void) { return (storage_type() & _BASE_TYPE_MASK) == _BASE_TYPE_NVME; } ``` Then we can use `storage_is_nvme` here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Gerrit-Change-Number: 85828 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 02:30:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Andy Hsu, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: @yupingso@google.com Hi yuping, Please help review this patch. Thank you. -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 02:02:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: @yupingso@google.com Hi yuping, Please help review this patch. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 02:01:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Work around DPR silicon bug
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Work around DPR silicon bug ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 01:42:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Xeon ICX-SP support
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85845?usp=email ) Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85845/comment/169d5656_645287ba?us… : PS3, Line 9: Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested ICX is 3rd gen https://review.coreboot.org/c/coreboot/+/85845/comment/7e90eed9_49aa8d78?us… : PS3, Line 10: are dual socket systems with a LBG PCH. So this is tested on a real ICX-SP hardware? -- To view, visit https://review.coreboot.org/c/coreboot/+/85845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Gerrit-Change-Number: 85845 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 01:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Work around FSP bug
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Patrick Rudolph, Paul Menzel. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85789?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: cpu/x86/64bit/mode_switch: Work around FSP bug ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/64bit/mode_switch.S: https://review.coreboot.org/c/coreboot/+/85789/comment/156b9503_5d13f8f1?us… : PS3, Line 50: lidt -16(%ebp) should it be lidt (%ebp)? (per ln22-27) -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 06 Jan 2025 01:28:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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