coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Bora Guvendik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers. Hello Intel coreboot Reviewers, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86215?usp=email to look at the new patch set (#2). Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... drivers/soc/cse: Fix overflow in CSE telemetry calculation MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow. Here is an example, if cse_perf_data.timestamp[i] value is 4304903 milliseconds. When multiplied by 1000 to convert to microseconds, the value becomes 0x979B58 instead of 0x100979B58. TEST=Boot to OS Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/cse/telemetry.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/86215/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[XS] Change in coreboot[main]: drivers/soc/cse: Fix overflow in CSE telemetry calculation
by Bora Guvendik (Code Review) 29 Jan '25

29 Jan '25

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86215?usp=email ) Change subject: drivers/soc/cse: Fix overflow in CSE telemetry calculation ...................................................................... drivers/soc/cse: Fix overflow in CSE telemetry calculation MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow. Here is an example, if cse_perf_data.timestamp[i] value is 4304903 milliseconds. When multiplied by 1000 to convert to microseconds, the value becomes 0x979B58 instead of 0x100979B58. TEST=Boot to OS Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/cse/telemetry.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/86215/1 diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 2c9fb54..62814eb 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -4,7 +4,7 @@ #include <intelblocks/cse.h> #include <timestamp.h> -#define MSEC_TO_USEC(x) (x * 1000) +#define MSEC_TO_USEC(x) ((s64)x * 1000) enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3 Gerrit-Change-Number: 86215 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brya/var/craaskov: Add/select VBT
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86214?usp=email ) Change subject: mb/google/brya/var/craaskov: Add/select VBT ...................................................................... mb/google/brya/var/craaskov: Add/select VBT Add VBT data file for crasskov, and enable its use by selecting INTEL_GMA_HAVE_VBT. VBT extracted from stock firmware image Google_Craaskov.15217.616.0; it has BDB version 2.51, which matches the current FSP binaries. TEST=build/boot craaskov with edk2 payload Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/craaskov/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86214/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d32435b..dfa571e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -201,6 +201,7 @@ config BOARD_GOOGLE_CRAASKOV select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_CONSTITUTION diff --git a/src/mainboard/google/brya/variants/craaskov/data.vbt b/src/mainboard/google/brya/variants/craaskov/data.vbt new file mode 100644 index 0000000..c47b424 --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/86214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b Gerrit-Change-Number: 86214 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Angel Pons (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Jérémy Compostella, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/85639/comment/f0b66bbe_fba80f16?us… : PS1, Line 280: uint8_t > maybe 'cache_id'? or is that too redundant? I was thinking of `unique_id`, but I'm okay with `cache_id` too. Aside, if we're making this field a `uint16_t`, I would suggest placing it earlier for alignment reasons: ``` struct cpu_cache_info { uint8_t type; uint8_t level; uint16_t cache_id; size_t num_ways; size_t num_sets; size_t line_size; size_t size; size_t physical_partitions; size_t num_cores_shared; bool fully_associative; }; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 15:14:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info
by Felix Held (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Angel Pons, Jérémy Compostella, Naresh Solanki, Patrick Rudolph, Paul Menzel. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Update cache info ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: how common is this code? i'd expect this to not only be correct for glinda; not sure though if this will be correct for all amd non-car socs -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 15:10:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Felix Held (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Jérémy Compostella, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/85639/comment/eae25073_b0d5d06e?us… : PS1, Line 280: uint8_t > Since its purpose is to uniquely identify a particular cache, I feel cache_id should be fine & pleas […] maybe 'cache_id'? or is that too redundant? -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 15:07:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/starlabs/*: Correct configuration of GPIOs used in ACPI
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86205?usp=email ) Change subject: mb/starlabs/*: Correct configuration of GPIOs used in ACPI ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562 Gerrit-Change-Number: 86205 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 29 Jan 2025 15:02:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct HDA Subsystem ID
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86212?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct HDA Subsystem ID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098 Gerrit-Change-Number: 86212 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 29 Jan 2025 15:00:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/chipset.cb: Update for glinda
by Patrick Rudolph (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Maximilian Brune. Patrick Rudolph has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84376?usp=email ) Change subject: soc/amd/glinda/chipset.cb: Update for glinda ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/glinda/chipset.cb: https://review.coreboot.org/c/coreboot/+/84376/comment/cc901d8d_736d9fc0?us… : PS6, Line 47: gpp_bridge_b Breaks ACPI PM timer since the PPB is no longer properly configured. Either the device needs to be hidden by ramstage code or be always on. -- To view, visit https://review.coreboot.org/c/coreboot/+/84376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Gerrit-Change-Number: 84376 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ana Cabral Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 14:58:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/*: Correct/set UserBd in romstage
by Matt DeVillier (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86206?usp=email ) Change subject: mb/starlabs/*: Correct/set UserBd in romstage ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: what effect does this have in terms of FSP programming? -- To view, visit https://review.coreboot.org/c/coreboot/+/86206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c21cc30a0cfc1dccc3f9863e8f3d522afdf31a Gerrit-Change-Number: 86206 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 29 Jan 2025 14:56:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025