coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:44:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:44:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 7: Code-Review+2 (2 comments) File src/soc/mediatek/mt8196/gpueb.c: https://review.coreboot.org/c/coreboot/+/85654/comment/ee1c5d50_60abfa6a?us… : PS7, Line 204: Failed to parse load buffer Buffer size too small https://review.coreboot.org/c/coreboot/+/85654/comment/65dff507_ebd8f260?us… : PS7, Line 233: { remove -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Ariel Otilibili. Shuo Liu has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85786?usp=email ) Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Helllo @shuo.liu@intel.com; thanks for having looked at the patch. […] Hi Ariel, LGTM and please check with others. -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Mon, 06 Jan 2025 06:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ariel Otilibili

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85809?usp=email ) Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/ebg/soc_xhci.c: https://review.coreboot.org/c/coreboot/+/85809/comment/ef3aef40_44ceb28d?us… : PS3, Line 21: When get_xhci_bar is called, the initial mapping is assumed to be mapped by FSP and not coreboot here, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/85809?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5 Gerrit-Change-Number: 85809 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:37:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize clkbuf and srclken in romstage
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85843?usp=email ) Change subject: mb/google/rauru: Initialize clkbuf and srclken in romstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a6f93d3ec27944bea72bbadf95a03a54a8a0662 Gerrit-Change-Number: 85843 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:36:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Make use of PCI driver for xHCI
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85808?usp=email ) Change subject: soc/intel/xeon_sp: Make use of PCI driver for xHCI ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/xeon_sp/ebg/soc_xhci.c: https://review.coreboot.org/c/coreboot/+/85808/comment/896078a3_61a2fa27?us… : PS3, Line 52: Maybe add a comment to indicate it will be called at src/soc/intel/common/block/xhci/xhci.c? -- To view, visit https://review.coreboot.org/c/coreboot/+/85808?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3968da4c95febbb270e1dbbea8b8b1b8fc1e96d Gerrit-Change-Number: 85808 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... Patch Set 1: (28 comments) File src/soc/mediatek/mt8196/include/soc/srclken_rc.h: https://review.coreboot.org/c/coreboot/+/85842/comment/961cd70d_a154723c?us… : PS1, Line 16: = 5 Remove these. https://review.coreboot.org/c/coreboot/+/85842/comment/c5995b41_2bb455f3?us… : PS1, Line 126: _M What do `_M` and `_B` mean here? If that means MASK, and we remove `_M` and `_MSK_B`? https://review.coreboot.org/c/coreboot/+/85842/comment/7de474e3_810b034d?us… : PS1, Line 184: struct mtk_rc_status_regs { Merge this into the `mtk_rc_regs` struct. Remove `RC_STATE_BASE`. https://review.coreboot.org/c/coreboot/+/85842/comment/eb439e7e_552fdaf7?us… : PS1, Line 202: Remove 2 tabs File src/soc/mediatek/mt8196/srclken_rc.c: https://review.coreboot.org/c/coreboot/+/85842/comment/99ef6135_45dfb346?us… : PS1, Line 32: ~= spaces around `~=` https://review.coreboot.org/c/coreboot/+/85842/comment/7b066acc_361f2a04?us… : PS1, Line 135: Remove extra blank line. https://review.coreboot.org/c/coreboot/+/85842/comment/366496ff_73764c68?us… : PS1, Line 167: #define CHN_MASK (BIT(CHN_DCXO_L) | BIT(CHN_DCXO_H)) : #define CHN_NOT_SUPPORT(i) (BIT(i) & CHN_MASK) For `CHN_NOT_SUPPORT`, `INIT_SUBSYS_FPM2LPM` and `INIT_SUBSYS_TO_HW`, can we change them to an configuration array? ``` static const struct { bool disabled; bool lpm; bool hw_mode; } rc_config[MAX_CHN_NUM] = { [CHN_SUSPEND] = ..., ... [CHN_GPS] = { .lpm = true, .hw_mode = true }, ... [CHN_DCXO_L] = { .disabled = true }, ... }; ``` Alternatively, we can change them to 3 functions: `chn_supported()`, `chn_is_lpm()`, `chn_is_hw_mode()`. https://review.coreboot.org/c/coreboot/+/85842/comment/a3ead1ac_2c0e7acb?us… : PS1, Line 182: * space https://review.coreboot.org/c/coreboot/+/85842/comment/0844bc36_2697c832?us… : PS1, Line 203: XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN `XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN` can be moved to the `SUB_CTRL_CON_UNUSE` macro definition. https://review.coreboot.org/c/coreboot/+/85842/comment/73eba65c_d2c562ec?us… : PS1, Line 225: RG What does RG mean? https://review.coreboot.org/c/coreboot/+/85842/comment/30ca540f_9a3ada71?us… : PS1, Line 265: code flow ASSERT already What does this mean? https://review.coreboot.org/c/coreboot/+/85842/comment/e662b25b_3472fd44?us… : PS1, Line 273: ASSERT assert Same below. https://review.coreboot.org/c/coreboot/+/85842/comment/d598e4fa_bdb64af2?us… : PS1, Line 276: INIT_MODE Can we split `INIT_MODE` to a separate function `rc_ctrl_mode_init`? Then `INIT_MODE` enum value can also be removed. https://review.coreboot.org/c/coreboot/+/85842/comment/aca14355_9bad0d88?us… : PS1, Line 278: rc_ctrl[id] Use a local variable (const pointer) for `rc_ctrl[id]`. https://review.coreboot.org/c/coreboot/+/85842/comment/421c63b7_5bbbd07a?us… : PS1, Line 312: else : return; > ``` […] ``` assert(mode == SW_FPM_HIGH || mode == SW_FPM_LOW); int fpm = SW_FPM_HIGH ? 1 : 0; SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, fpm); ``` https://review.coreboot.org/c/coreboot/+/85842/comment/c194ee59_ef16db2b?us… : PS1, Line 315: rc_ctrl[id].sw_fpm = mode; Can we change `rc_ctrl` const and NOT modify it here? In line #511, we can still get the current fpm value by: ``` unsigned int fpm = rc_ctrl[ch].sw_fpm; if (rc_config[ch].lpm) fpm = SW_FPM_LOW; ``` https://review.coreboot.org/c/coreboot/+/85842/comment/216d58b2_f7bce42b?us… : PS1, Line 346: rc_ctrl_mode_switch_init Adjust the order of these 3 functions: rc_ctrl_mode_switch_init -> rc_init_subsys_lpm -> rc_init_subsys_hw_mode. https://review.coreboot.org/c/coreboot/+/85842/comment/9f5ed530_e5fa57e2?us… : PS1, Line 357: unsigned int state `u32 mask, u32 value` Pass `mask` (0xA) from the caller. https://review.coreboot.org/c/coreboot/+/85842/comment/4378527e_dae01ed0?us… : PS1, Line 357: unsigned int chn `enum chn_id id` https://review.coreboot.org/c/coreboot/+/85842/comment/ec6f4ca8_f765f438?us… : PS1, Line 360: INFO ERROR https://review.coreboot.org/c/coreboot/+/85842/comment/62a784c7_8a4ca796?us… : PS1, Line 378: e E https://review.coreboot.org/c/coreboot/+/85842/comment/42dee60b_072b1dc7?us… : PS1, Line 385: dsb > coreboot read/write APIs already include `dmb()`. […] I have the same question. https://review.coreboot.org/c/coreboot/+/85842/comment/bd517e6d_21d864b3?us… : PS1, Line 401: e E https://review.coreboot.org/c/coreboot/+/85842/comment/1f12f5dd_2ff63a8a?us… : PS1, Line 414: _BF_VALUE `_BF_VALUE` isn't part of the API, so it should never be used. Please use `WRITE32_BITFIELDS`. https://review.coreboot.org/c/coreboot/+/85842/comment/1325ab0a_dd6f3563?us… : PS1, Line 477: u U https://review.coreboot.org/c/coreboot/+/85842/comment/cc48333e_bd1caf13?us… : PS1, Line 514: ret Should return -1 at the end of function if one of the channel fails. Right now we store the return value of the *last* channel, which is wrong. https://review.coreboot.org/c/coreboot/+/85842/comment/50f91f98_46dcac2f?us… : PS1, Line 515: ASSERT(!ret); We shouldn't use assertions for run-time errors. When this fails, should we continue to boot or not? 1. If so, then return -1 here. 2. If not, call `die("...")`. https://review.coreboot.org/c/coreboot/+/85842/comment/57f7b5f3_a8d7f73e?us… : PS1, Line 537: w W -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:35:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Naveen M (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Mac Chiang, Pranava Y N, Weimin Wu. Naveen M has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85571/comment/6be345a3_2c56139e?us… : PS2, Line 13: static struct soundwire_multilane alc711_multilane = { : }; > @Naveen , can you please help here ? understanding the original query from subrata, since there is a struct alc711_multilane defined, whether config->multilane.lane_mapping default values can be made so that when chip detection fails, it will fallback to those default values. Actually default should always be SINGLE_LANE, if kernel doesn't get the configurations for "mipi-sdw-lane-%d-mapping" properties. per soundwire driver team recommendation, there shouldn't be any default values for multi-lane, as it depends on the H/W design. -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 06:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com> Comment-In-Reply-To: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85859?usp=email to look at the new patch set (#3). Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8186/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 13 files changed, 84 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit January 2025