coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: arch/x86: Replace 'unsigned long int' by 'unsigned long'
by Maximilian Brune (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Ariel Otilibili, Felix Singer, Nicholas Chin. Maximilian Brune has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85782?usp=email ) Change subject: arch/x86: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: building with BUILD_TIMELESS shows there is no difference in the binaries. -- To view, visit https://review.coreboot.org/c/coreboot/+/85782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Gerrit-Change-Number: 85782 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ariel Otilibili Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 11:42:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
by Maximilian Brune (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Ariel Otilibili. Maximilian Brune has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85786?usp=email ) Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Mon, 06 Jan 2025 11:37:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rauru: Add ALC5650 support
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Xinxiong Xu, Yang Wu. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85858?usp=email ) Change subject: mb/google/rauru: Add ALC5650 support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988 Gerrit-Change-Number: 85858 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 10:44:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Xeon ICX-SP support
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85845?usp=email ) Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85845/comment/8a488332_805faa66?us… : PS3, Line 9: Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested > ICX is 3rd gen ICX might be advertised as 3rd gen Xeon-SP, but this term is intentionally not used as CPX is also 3rd gen Xeon-SP. ICX 1st gen 10nm Xeon-SP SPR 2nd gen 10nm Xeon-SP EMR 3rd gen 10nm Xeon-SP https://review.coreboot.org/c/coreboot/+/85845/comment/4cd00883_b4512529?us… : PS3, Line 10: are dual socket systems with a LBG PCH. > So this is tested on a real ICX-SP hardware? Yes. Mainboard support will be added as separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/85845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Gerrit-Change-Number: 85845 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 10:38:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for...
by Mario Scheithauer (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Werner Zeh. Hello Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85864?usp=email to look at the new patch set (#2). Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 ...................................................................... mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 The latest patch chain for mc_ehl5, commit 2d9a82cf8a57 ("mb/siemens/mc_ehl5: Rename SDIO converge layer register defines") and following patches, have simplified the SD card code. This patch now adapts the other mc_ehl mainboards accordingly to standardize the code. Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c 3 files changed, 53 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85864/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Gerrit-Change-Number: 85864 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for...
by Mario Scheithauer (Code Review) 06 Jan '25

06 Jan '25

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85864?usp=email ) Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 ...................................................................... mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 The latest patch chain for mc_ehl5, commit 2d9a82cf8a57 ("mb/siemens/mc_ehl5: Rename SDIO converge layer register defines") and following patches, have simplified the SD card code. This patch now adapts the other mc_ehl mainboards accordingly to standardize the code. Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c 3 files changed, 56 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85864/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index 1121399..dd90d6f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -10,12 +10,21 @@ #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { @@ -30,26 +39,16 @@ if (dev) pci_write_config8(dev, 0xd8, 0x3e); - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { - uint32_t reg; - uint16_t reg16; struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); - /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ - reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); - reg |= SD_CAP_BYP_DDR50; - write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ - reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); - reg16 |= HOSTCTRL2_PRESET; - write16(res2mmio(res, HOSTCTRL2, 0), reg16); + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index ca52e7b..d76ac03 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -2,43 +2,44 @@ #include <baseboard/variants.h> #include <bootstate.h> -#include <device/mmio.h> +#include <device/pci_ids.h> #include <gpio.h> +#include <intelblocks/pcr.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { struct device *dev; - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { - uint32_t reg; - uint16_t reg16; struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); - /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ - reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); - reg |= SD_CAP_BYP_DDR50; - write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ - reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); - reg16 |= HOSTCTRL2_PRESET; - write16(res2mmio(res, HOSTCTRL2, 0), reg16); + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c index 8accade..3ef72fd 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -9,28 +9,33 @@ #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 -#define SD_CAP_BYP_SDR50 (1 << 13) -#define SD_CAP_BYP_SDR104 (1 << 14) -#define SD_CAP_BYP_DDR50 (1 << 15) +#define MMC_CAP_BYP 0x810 +#define MMC_CAP_BYP_EN 0x5A +#define MMC_CAP_BYP_REG1 0x814 +#define MMC_CAP_BYP_SDR50 (1 << 13) +#define MMC_CAP_BYP_SDR104 (1 << 14) +#define MMC_CAP_BYP_DDR50 (1 << 15) + +/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ +static void disable_sdr_modes(struct resource *res) +{ + write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN); + clrsetbits32(res2mmio(res, MMC_CAP_BYP_REG1, 0), + MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50, + MMC_CAP_BYP_DDR50); +} void variant_mainboard_final(void) { struct device *dev; - /* Limit SD card speed to DDR50 mode to avoid SDR104/SDR50 modes due to - layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - clrsetbits32(res2mmio(res, SD_CAP_BYP_REG1, 0), - SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50, - SD_CAP_BYP_DDR50); + + disable_sdr_modes(res); /* Use preset driver strength from preset value registers. */ clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); -- To view, visit https://review.coreboot.org/c/coreboot/+/85864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Gerrit-Change-Number: 85864 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85859?usp=email ) Change subject: soc/mediatek: Rename DP related header files ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85859/comment/851356ff_35446ed2?us… : PS3, Line 11: difition > definition Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Jan 2025 09:31:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85859?usp=email to look at the new patch set (#4). Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register definition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8186/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 13 files changed, 84 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... Patch Set 3: (11 comments) File src/soc/mediatek/common/dp/dptx.c: https://review.coreboot.org/c/coreboot/+/85860/comment/ccdd3037_fad7fe74?us… : PS3, Line 15: dptx_link_train_clock_recovery_delay Looks the same as mt8196's `drm_dp_link_train_clock_recovery_delay`, except that in the edge case (`rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14`) the delay is different (1ms vs 100us). We may ask MTK if the delay can be unified. https://review.coreboot.org/c/coreboot/+/85860/comment/e395533f_b7ed0884?us… : PS3, Line 32: dptx_link_train_channel_eq_delay Same here. https://review.coreboot.org/c/coreboot/+/85860/comment/ef41d056_107cc72a?us… : PS3, Line 49: dptx_channel_eq_ok Looks the same as mt8196's `drm_dp_channel_eq_ok`. https://review.coreboot.org/c/coreboot/+/85860/comment/19d98c1b_5b7aa9e1?us… : PS3, Line 425: dptx_set_trainingstart I think it's also possible to share this with mt8196. The differences are: 1. MT8196 has an extra `dptx_hal_setscramble` call 2. MT8196 doesn't have the `DP_LINKRATE_HBR25` case 3. Common code's `dptx_trainingflow` vs MT8196's `mtk_edp_train_setting + mtk_edp_train_cr + mtk_edp_train_eq` For #3, `dptx_trainingflow` has a while loop containing calls to `dptx_train_tps1` and `dptx_train_tps2_3`, and I think we can split that into two loops, one for `tps1` (equivalent to mt8196's `mtk_edp_train_cr`) and the other for `tps2_3` (equivalent to mt8196's `mtk_edp_train_eq`). If you think it's too difficult to share this function, I'm fine with the correct approach. https://review.coreboot.org/c/coreboot/+/85860/comment/d9fbc6a0_ffd8e379?us… : PS3, Line 536: static void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable) Looks the same as mt8196. https://review.coreboot.org/c/coreboot/+/85860/comment/9a6172c5_a9c47491?us… : PS3, Line 559: dptx_video_config Can this be shared with mt8196? File src/soc/mediatek/common/dp/include/soc/dptx_common.h: https://review.coreboot.org/c/coreboot/+/85860/comment/0bc24288_cb931bfb?us… : PS3, Line 50: DP_LANE_CHANNEL_EQ_DONE | \ align https://review.coreboot.org/c/coreboot/+/85860/comment/8366e7c0_f1d4140d?us… : PS3, Line 107: tabs https://review.coreboot.org/c/coreboot/+/85860/comment/f8e18c5e_53ff3b3a?us… : PS3, Line 214: dptx_get_lane_status If `dptx_channel_eq_ok` is shared with mt8196, then this can be static. https://review.coreboot.org/c/coreboot/+/85860/comment/8a288dc7_a380254c?us… : PS3, Line 217: bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, `dptx_auxwrite_bytes` and `dptx_auxread_bytes` can be static functions. https://review.coreboot.org/c/coreboot/+/85860/comment/59413120_69756504?us… : PS3, Line 221: void dptx_videomute(struct mtk_dp *mtk_dp, bool enable); : void dptx_set_dptxout(struct mtk_dp *mtk_dp); These 2 functions can be static if `dptx_video_enable` is shared with mt8196. -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 09:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
by Shuo Liu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85809?usp=email ) Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/xeon_sp/ebg/soc_xhci.c: https://review.coreboot.org/c/coreboot/+/85809/comment/cbb5ad09_f2e580fb?us… : PS3, Line 21: > PCI resource allocation is done by FSP and it assignes BAR in high MMIO while coreboot defaults to l […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85809?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5 Gerrit-Change-Number: 85809 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 09:25:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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coreboot-gerrit January 2025