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[XS] Change in coreboot[main]: mb/starlabs/*: Explicitly set Early Command Training
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86207?usp=email ) Change subject: mb/starlabs/*: Explicitly set Early Command Training ...................................................................... mb/starlabs/*: Explicitly set Early Command Training Explicitly set ECT in romstage; enable it for boards that use LPxxx memory and disable it for boards that use SODIMMs. Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c M src/mainboard/starlabs/starbook/variants/adl/romstage.c M src/mainboard/starlabs/starbook/variants/adl_n/romstage.c M src/mainboard/starlabs/starbook/variants/cml/romstage.c M src/mainboard/starlabs/starbook/variants/mtl/romstage.c M src/mainboard/starlabs/starbook/variants/rpl/romstage.c M src/mainboard/starlabs/starbook/variants/tgl/romstage.c 7 files changed, 7 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c index 530246a..5f8ebd6 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .ect = false, .UserBd = BOARD_TYPE_ULT_ULX, }; diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c index d31c63e..98683da 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .ect = false, .UserBd = BOARD_TYPE_MOBILE, }; diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c index 2f1d1a2b..21000d1 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .ect = false, .UserBd = BOARD_TYPE_ULT_ULX, }; diff --git a/src/mainboard/starlabs/starbook/variants/cml/romstage.c b/src/mainboard/starlabs/starbook/variants/cml/romstage.c index 372f8b0..648943b 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/cml/romstage.c @@ -66,7 +66,7 @@ .rcomp_targets = {100, 40, 20, 20, 26}, .dq_pins_interleaved = 0, .vref_ca_config = 2, - .ect = 0, + .ect = true, }; const uint8_t vtd = get_uint_option("vtd", 1); diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index 64b7884..3181865 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR5, + .ect = false, .UserBd = BOARD_TYPE_MOBILE, }; diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c index a4261e7..20d518c 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .ect = false, .UserBd = BOARD_TYPE_MOBILE, }; diff --git a/src/mainboard/starlabs/starbook/variants/tgl/romstage.c b/src/mainboard/starlabs/starbook/variants/tgl/romstage.c index ceeb754..8eb82a5 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .ect = false, }; const bool half_populated = false; -- To view, visit https://review.coreboot.org/c/coreboot/+/86207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036 Gerrit-Change-Number: 86207 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/*: Explicitly set Early Command Training
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86207?usp=email ) Change subject: mb/starlabs/*: Explicitly set Early Command Training ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036 Gerrit-Change-Number: 86207 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Jan 2025 08:46:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/*: Correct/set UserBd in romstage
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86206?usp=email ) Change subject: mb/starlabs/*: Correct/set UserBd in romstage ...................................................................... mb/starlabs/*: Correct/set UserBd in romstage Change-Id: Id0c21cc30a0cfc1dccc3f9863e8f3d522afdf31a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86206 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c M src/mainboard/starlabs/starbook/variants/adl/romstage.c M src/mainboard/starlabs/starbook/variants/adl_n/romstage.c M src/mainboard/starlabs/starbook/variants/mtl/romstage.c M src/mainboard/starlabs/starbook/variants/rpl/romstage.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c 6 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c index 502411b..530246a 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .UserBd = BOARD_TYPE_ULT_ULX, }; const bool half_populated = true; diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c index 17629b4..d31c63e 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .UserBd = BOARD_TYPE_MOBILE, }; const bool half_populated = false; diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c index 2130010..2f1d1a2b 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .UserBd = BOARD_TYPE_ULT_ULX, }; const bool half_populated = true; diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index beb623c..64b7884 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR5, + .UserBd = BOARD_TYPE_MOBILE, }; const bool half_populated = false; diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c index e7e1c6a..a4261e7 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c @@ -9,6 +9,7 @@ { const struct mb_cfg mem_config = { .type = MEM_TYPE_DDR4, + .UserBd = BOARD_TYPE_MOBILE, }; const bool half_populated = false; diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c index b346241..235a8b4 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c @@ -81,7 +81,7 @@ }, .ect = true, - .UserBd = BOARD_TYPE_MOBILE, + .UserBd = BOARD_TYPE_ULT_ULX, .LpDdrDqDqsReTraining = true, .lp5x_config = { -- To view, visit https://review.coreboot.org/c/coreboot/+/86206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c21cc30a0cfc1dccc3f9863e8f3d522afdf31a Gerrit-Change-Number: 86206 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Correct configuration of GPIOs used in ACPI
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86205?usp=email ) Change subject: mb/starlabs/*: Correct configuration of GPIOs used in ACPI ...................................................................... mb/starlabs/*: Correct configuration of GPIOs used in ACPI Correct, and unify, the configuration of the GPIOs use in ACPI for enabling and resetting: * Make all GPIOs host owned * Set enable GPIOs to DEEP * Set reset GPIOs to PLTRST Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86205 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c M src/mainboard/starlabs/starbook/variants/mtl/gpio.c M src/mainboard/starlabs/starbook/variants/rpl/gpio.c M src/mainboard/starlabs/starbook/variants/tgl/gpio.c M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 8 files changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 6ae686a..f4d7ab0 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -229,7 +229,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE), /* D17: Not Connected */ PAD_NC(GPP_D17, NONE), /* D18: Not Connected */ @@ -340,7 +340,7 @@ PAD_NC(GPP_F23, NONE), /* H0: PCH M.2 SSD Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE), /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* H2: Wireless LAN Reset */ diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index ec32e83..21821be 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -228,7 +228,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE), /* D17: Not used Fingerprint ID */ PAD_NC(GPP_D17, NONE), /* D18: Not Connected */ @@ -339,11 +339,11 @@ PAD_NC(GPP_F23, NONE), /* H0: PCH M.2 SSD Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE), /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H2: Wireless LAN Reset */ - PAD_CFG_GPO(GPP_H2, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE), /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), /* H4: I2C 0 SDA Touchpad */ diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 79a4c4c..b59ad9d 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -228,7 +228,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE), /* D17: Not used Fingerprint ID */ PAD_NC(GPP_D17, NONE), /* D18: Not Connected */ @@ -339,11 +339,11 @@ PAD_NC(GPP_F23, NONE), /* H0: PCH M.2 SSD Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE), /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H2: Wireless LAN Reset */ - PAD_CFG_GPO(GPP_H2, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE), /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), /* H4: I2C 0 SDA Touchpad */ diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index 943998c..b3ed9e2 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -248,14 +248,14 @@ * End: GPP_H23 */ /* H00: M.2_PCH_SSD_RESET_N */ - PAD_CFG_GPO(GPP_H00, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H00, 1, PLTRST, NONE), /* H01: FLASH RECOVERY * HIGH: ENABLED * LOW: DISABLED * WEAK INTERNAL PD 20K */ PAD_NC(GPP_H01, NONE), /* H02: WLAN_RST_N */ - PAD_CFG_GPO(GPP_H02, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H02, 1, PLTRST, NONE), /* H03: */ PAD_NC(GPP_H03, NONE), /* H04: */ @@ -265,7 +265,7 @@ /* H06: */ PAD_NC(GPP_H06, NONE), /* H07: M.2_CPU_SSD_PWREN */ - PAD_CFG_GPO(GPP_H07, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H07, 1, DEEP, NONE), /* H08: */ PAD_NC(GPP_H08, NONE), /* H09: */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index a17c00f..e8c2550 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -224,7 +224,7 @@ /* D13: Wireless LAN Wake */ PAD_NC(GPP_D13, NONE), /* D14: CPU M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D14, 1, DEEP, NONE), /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ @@ -245,7 +245,7 @@ /* E3: WiFi RF Kill */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Retimer Force Power */ - PAD_CFG_GPO(GPP_E4, 0, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E4, 0, DEEP, NONE), /* E5: Not Connected */ PAD_NC(GPP_E5, NONE), /* E6: JTAG ODT No internal PD @@ -330,7 +330,7 @@ /* F19: Not Connected */ PAD_NC(GPP_F19, NONE), /* F20: CPU M.2 SSD Reset */ - PAD_CFG_GPO(GPP_F20, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F20, 1, PLTRST, NONE), /* F21: GPPC_F21 */ PAD_NC(GPP_F21, NONE), /* F22: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 1ba1b81..f1350c5 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -66,7 +66,7 @@ /* A10: WLAN_PCM_IN */ PAD_NC(GPP_A10, NONE), /* A11: M2_CPU_SSD_RST_N */ - PAD_CFG_GPO(GPP_A11, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A11, 1, PLTRST, NONE), /* A12: SATAGP_1 */ PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* A13: Not Connected */ @@ -90,7 +90,7 @@ /* A22: Not Connected */ PAD_NC(GPP_A22, NONE), /* A23: TC_RETIMER_FORCE_PWR */ - PAD_CFG_GPO(GPP_A23, 0, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A23, 0, DEEP, NONE), /* B0: CORE_VID_0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -219,7 +219,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: CPU_SSD_PWREN */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE), /* D17: Not Connected */ PAD_NC(GPP_D17, NONE), /* D18: Not Connected */ diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index 23ca3e5..e0e6164 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -229,7 +229,7 @@ /* D13: Wireless LAN Wake */ PAD_NC(GPP_D13, NONE), /* D14: CPU M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D14, 1, DEEP, NONE), /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ @@ -250,7 +250,7 @@ /* E3: WiFi RF Kill */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Retimer Force Power */ - PAD_CFG_GPO(GPP_E4, 0, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E4, 0, DEEP, NONE), /* E5: Not Connected */ PAD_NC(GPP_E5, NONE), /* E6: JTAG ODT No internal PD @@ -327,7 +327,7 @@ /* F19: Not Connected */ PAD_NC(GPP_F19, NONE), /* F20: CPU M.2 SSD Reset */ - PAD_CFG_GPO(GPP_F20, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F20, 1, PLTRST, NONE), /* F21: GPPC_F21 */ PAD_NC(GPP_F21, NONE), /* F22: Not Connected */ @@ -340,7 +340,7 @@ /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H2: Wireless LAN Reset */ - PAD_CFG_GPO(GPP_H2, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, PLTRST, NONE), /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), /* H4: I2C 0 SDA Touchpad */ diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index 2ee5c67..0126a5d 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -227,7 +227,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D16, 1, DEEP, NONE), /* D17: Not used Fingerprint ID */ PAD_NC(GPP_D17, NONE), /* D18: Bluetooth Wake */ @@ -323,7 +323,7 @@ /* F16: Not Connected */ PAD_NC(GPP_F16, NONE), /* F17: Touch Panel Reset */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_F17, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F17, 1, PLTRST, NONE), /* F18: Touch Panel Interrupt */ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* F19: Not Connected */ @@ -338,7 +338,7 @@ PAD_NC(GPP_F23, NONE), /* H0: PCH M.2 SSD Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, PLTRST, NONE), /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H2: Wireless LAN Reset */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562 Gerrit-Change-Number: 86205 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct alignment in devicetree
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86204?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct alignment in devicetree ...................................................................... mb/starlabs/starbook/mtl: Correct alignment in devicetree Change-Id: I3017b4a79f044a7312520469fa185c355f3970c0 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index f53b549..86605ec 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -34,14 +34,14 @@ chip drivers/usb/acpi device ref tcss_root_hub on chip drivers/usb/acpi - register "desc" = ""USB Type-C"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB Type-C"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 1)" device ref tcss_usb3_port2 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3017b4a79f044a7312520469fa185c355f3970c0 Gerrit-Change-Number: 86204 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Unselect unused Kconfig values
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86203?usp=email ) Change subject: mb/starlabs/starbook/mtl: Unselect unused Kconfig values ...................................................................... mb/starlabs/starbook/mtl: Unselect unused Kconfig values This board does not have TBT 4, so unselect Kconfig values for it. Change-Id: Id13bb7fc1f9a8f00c10effeaf4b8e1970a173e36 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/Kconfig 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 5ba827c..b7e1c63 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -105,7 +105,6 @@ select BOARD_ROMSIZE_KB_32768 select BOARD_STARLABS_STARBOOK_SERIES select DRIVERS_INTEL_PMC - select DRIVERS_INTEL_USB4_RETIMER select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS select EC_STARLABS_LID_SWITCH @@ -119,7 +118,6 @@ select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CRASHLOG - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SPI_FLASH_WINBOND select TPM_MEASURED_BOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/86203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id13bb7fc1f9a8f00c10effeaf4b8e1970a173e36 Gerrit-Change-Number: 86203 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Configure CNVi Bluetooth I2S GPIOs
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86139?usp=email ) Change subject: mb/starlabs/byte_adl: Configure CNVi Bluetooth I2S GPIOs ...................................................................... mb/starlabs/byte_adl: Configure CNVi Bluetooth I2S GPIOs These pads are required for Audio Offload, so enable them to match the configuration in devicetree. Change-Id: I757b2c2f77edb21d0eb1a59e3e1eb81671b9929f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86139 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 3ea0629..6ae686a 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -465,6 +465,12 @@ PAD_NC(GPP_VGPIO_19, NONE), PAD_NC(GPP_VGPIO_20, NONE), PAD_NC(GPP_VGPIO_21, NONE), + + /* BT I2S */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I757b2c2f77edb21d0eb1a59e3e1eb81671b9929f Gerrit-Change-Number: 86139 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/byte_adl: Disable CNVi vUART Pins
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86138?usp=email ) Change subject: mb/starlabs/byte_adl: Disable CNVi vUART Pins ...................................................................... mb/starlabs/byte_adl: Disable CNVi vUART Pins This board is using the USB interface for Bluetooth so these can be disabled. Change-Id: I95c3d1607b62c899acdda6b3b3aae97067e6b266 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 92bc10d..3ea0629 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -453,6 +453,18 @@ /* BT_EN */ PAD_CFG_GPO_GPIO_DRIVER(GPP_VGPIO_0, 1, DEEP, NONE), + + /* CNVi BT UART0 */ + PAD_NC(GPP_VGPIO_6, NONE), + PAD_NC(GPP_VGPIO_7, NONE), + PAD_NC(GPP_VGPIO_8, NONE), + PAD_NC(GPP_VGPIO_9, NONE), + + /* CNVi UART0 */ + PAD_NC(GPP_VGPIO_18, NONE), + PAD_NC(GPP_VGPIO_19, NONE), + PAD_NC(GPP_VGPIO_20, NONE), + PAD_NC(GPP_VGPIO_21, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86138?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95c3d1607b62c899acdda6b3b3aae97067e6b266 Gerrit-Change-Number: 86138 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Set BT_EN to host owned
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86137?usp=email ) Change subject: mb/starlabs/byte_adl: Set BT_EN to host owned ...................................................................... mb/starlabs/byte_adl: Set BT_EN to host owned BT_EN (VGPIO_0) needs to be host-owned, so that the driver can control it during the reset procedure. Adjust it accordingly. Change-Id: I9acc7943de423c0ab441226c0fb4f437a10d2749 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index ae814f0..92bc10d 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -450,6 +450,9 @@ PAD_NC(GPP_R6, NONE), /* R7: Not Connected */ PAD_NC(GPP_R7, NONE), + + /* BT_EN */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_VGPIO_0, 1, DEEP, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9acc7943de423c0ab441226c0fb4f437a10d2749 Gerrit-Change-Number: 86137 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration
by Sean Rhodes (Code Review) 30 Jan '25

30 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86136?usp=email ) Change subject: mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration ...................................................................... mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration This GPIO is used as MODEM_CLKREQ, which is Native Function 1. Adjust the configuration accordingly. Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 4a6f38e..ae814f0 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -298,8 +298,8 @@ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* F4: CNV RF Reset */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5: Not used MODEM_CLKREQ */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F5: MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), /* F7: TBT LSX VCCIO Weak Internal PD 20K -- To view, visit https://review.coreboot.org/c/coreboot/+/86136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308 Gerrit-Change-Number: 86136 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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