coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: arch/x86: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85782?usp=email ) Change subject: arch/x86: Replace 'unsigned long int' by 'unsigned long' ...................................................................... arch/x86: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Cc: "Jérémy Compostella" <jeremy.compostella(a)intel.com> Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85782 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/memset.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 142dda3..4ab07ed 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -12,7 +12,7 @@ void *memset(void *dstpp, int c, size_t len) { int d0; - unsigned long int dstp = (unsigned long int)dstpp; + unsigned long dstp = (unsigned long)dstpp; #if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Gerrit-Change-Number: 85782 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85786?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) File util/cbfstool/flashmap/fmap.c: https://review.coreboot.org/c/coreboot/+/85786/comment/20b406a9_219ef668?us… : PS1, Line 99: unsigned long offset = -1; If it is unsigned, how it is = -1 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 08 Jan 2025 02:56:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the argument type of MT6363
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85839?usp=email ) Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363 ...................................................................... soc/mediatek/mt8196: Correct the argument type of MT6363 Correct the argument type of the mt6363_sdmadc_read API and the return value type of the mt6363_read16 API. TEST=Build pass BUG=b:317009620 Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85839 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/boardid.c M src/soc/mediatek/common/include/soc/mt6363.h M src/soc/mediatek/common/include/soc/mt6363_sdmadc.h M src/soc/mediatek/common/mt6363.c M src/soc/mediatek/common/mt6363_sdmadc.c 5 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index e3e0979..fc0230d 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -38,7 +38,7 @@ static uint32_t get_adc_index(unsigned int channel) { - int value; + u32 value; mt6363_sdmadc_read(channel, &value, SDMADC_OPEN, AUXADC_VAL_PROCESSED); assert(channel < ARRAY_SIZE(adc_voltages)); diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h index 19b23d4..4659119 100644 --- a/src/soc/mediatek/common/include/soc/mt6363.h +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -108,7 +108,7 @@ void mt6363_enable_vram_digrf(bool enable); void mt6363_enable_vram_mdfe(bool enable); void mt6363_init_pmif_arb(void); -u32 mt6363_read16(u32 reg); +u16 mt6363_read16(u32 reg); void mt6363_write8(u32 reg, u8 reg_val); void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); void mt6363_init_setting(void); diff --git a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h index ae990c9..8735824 100644 --- a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h +++ b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h @@ -84,7 +84,7 @@ } sdmadc_hw_info; }; -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, enum sdmadc_pures pures, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type); #endif /* __MT6363_SDMADC_H__ */ diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 20ef9f0..b16f6b1 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -25,7 +25,7 @@ }; static struct pmif *pmif_arb; -u32 mt6363_read16(u32 reg) +u16 mt6363_read16(u32 reg) { u16 rdata = 0; diff --git a/src/soc/mediatek/common/mt6363_sdmadc.c b/src/soc/mediatek/common/mt6363_sdmadc.c index eb4b978..647423d 100644 --- a/src/soc/mediatek/common/mt6363_sdmadc.c +++ b/src/soc/mediatek/common/mt6363_sdmadc.c @@ -61,11 +61,11 @@ _Static_assert(ARRAY_SIZE(mt6363_sdmadc_chan_specs) == AUXADC_CHAN_MAX, "Wrong array size for mt6363_sdmadc_chan_specs"); -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type) { u8 wdata; - u32 regval; + u16 regval; u32 elapsed = 0; const struct auxadc_chan_spec *chan; -- To view, visit https://review.coreboot.org/c/coreboot/+/85839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Gerrit-Change-Number: 85839 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 02:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Fix MT6363 buck5 enablement
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85838?usp=email ) Change subject: soc/mediatek/mt8196: Fix MT6363 buck5 enablement ...................................................................... soc/mediatek/mt8196: Fix MT6363 buck5 enablement The MT6363 buck5 API's mask and shift settings are incorrect, preventing the buck from being disabled. Resolve the issue by correcting these two values. BUG=b:365445188 TEST=build pass, check buck5 is power off after calling the mt6363_enable_buck5 API. Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85838 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/mt6363.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 691282b..20ef9f0 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -211,7 +211,7 @@ void mt6363_enable_buck5(bool enable) { - mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x7, 0); + mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x1, 7); } void mt6363_enable_vcn15(bool enable) -- To view, visit https://review.coreboot.org/c/coreboot/+/85838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5 Gerrit-Change-Number: 85838 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface ...................................................................... soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface The initialization process of SPMI requires a certain amount of time (0.5ms) to ensure all components are correctly configured and synchronized. Otherwise, if the SPMI calibration fails, it will result in the non-serial firmware failing to boot. TEST=Build pass, non-serial firmware boot ok. BUG=b:341054056 Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index d00afe1..e646816 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <console/console.h> +#include <delay.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> @@ -285,6 +286,7 @@ { write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN); write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN); + udelay(500); printk(BIOS_INFO, "%s done\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/common/include/soc/storage.h: https://review.coreboot.org/c/coreboot/+/85878/comment/42fcba7f_79753672?us… : PS2, Line 11: 0x0 > Just noticed that `_BASE_TYPE(x)` would return UFS for `STORAGE_UNKNOWN`. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 02:51:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85878?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... soc/mediatek/common: Get storage type from mainboard Add common definitions and `mainboard_get_storage_type` API for determining the storage type from mainboard. TEST=emerge-rauru coreboot Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- A src/soc/mediatek/common/include/soc/storage.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85878/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: drivers/uart: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85784?usp=email ) Change subject: drivers/uart: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1416a2f7d75a888dcaf0775894aced981800866f Gerrit-Change-Number: 85784 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 08 Jan 2025 02:49:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long'
by Elyes Haouas (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Ariel Otilibili. Elyes Haouas has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85783?usp=email ) Change subject: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I940528dc4f8cb9b2d441d0f0d181cccebd315255 Gerrit-Change-Number: 85783 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Wed, 08 Jan 2025 02:49:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025