coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85860?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... soc/mediatek/common/dp: Move common functions to dptx_common.c Move the functions that can be shared with MT8196 to dptx_common.c. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx.c A src/soc/mediatek/common/dp/dptx_common.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 5 files changed, 645 insertions(+), 617 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85860/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
by Wonkyu Kim (Code Review) 07 Jan '25

07 Jan '25

Wonkyu Kim has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 04:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Determine PCIe init by storage_id
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85828?usp=email ) Change subject: mb/google/rauru: Determine PCIe init by storage_id ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85828/comment/4e5aae41_129cc8e8?us… : PS2, Line 52: return storage_id() == 3; > That's even better. I assume you meant […] That's it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Gerrit-Change-Number: 85828 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 04:01:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling pmif_spmi_enable_swinf
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling pmif_spmi_enable_swinf ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85799/comment/c9c8ac40_7d690acb?us… : PS4, Line 7: pmif_spmi_enable_swinf > Hi Yuping, […] Modify the commit subject to `Delay 0.5ms after enabling PMIF SPMI SW interface`. If that's too long, try `Delay 0.5ms after enabling PMIF SPMI`. -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 03:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Determine PCIe init by storage_id
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85828?usp=email ) Change subject: mb/google/rauru: Determine PCIe init by storage_id ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85828/comment/26f9fa30_6213928f?us… : PS2, Line 52: return storage_id() == 3; > I am thinking if we could follow pcie/regulator that has a `soc/storage. […] That's even better. I assume you meant ``` // soc/storage.h (shared for all SoCs) #define ... enum mtk_storage_type { }; // mb/google/BOARD/boardid.c enum mtk_storage_type mainboard_get_storage_type(void) { } ``` Then, `soc_init` will call `mainboard_get_storage_type()` and pass it to mtk-fsp. Is my understanding correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/85828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Gerrit-Change-Number: 85828 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 03:57:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling pmif_spmi_enable_swinf
by Jarried Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling pmif_spmi_enable_swinf ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85799/comment/fd6d4eb4_01063359?us… : PS4, Line 7: pmif_spmi_enable_swinf > In the other comment I was thinking about plain text. […] Hi Yuping, Sorry, I'm not quite sure what this comment is asking to modify. If you are asking about the meaning of 'swint', it indeed stands for SW interface. Or do you want to modify the commit subject to: Delay 0.5ms after enabling pmif spmi enable SW interface? thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 03:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Determine PCIe init by storage_id
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85828?usp=email ) Change subject: mb/google/rauru: Determine PCIe init by storage_id ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85828/comment/bba815b8_fb18a93f?us… : PS2, Line 52: return storage_id() == 3; > Can we modify `storage_type()` to return `enum storage_type` (by renaming `ufs_type`)? We could use […] I am thinking if we could follow pcie/regulator that has a `soc/storage.h` and a `mainboard_get_storage_type` API. We can also move above definitions to `soc/storage.h`. What do you think ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Gerrit-Change-Number: 85828 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 03:39:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Match VBT with SSFC
by Rui Zhou (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85875?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: Match VBT with SSFC ...................................................................... mb/google/nissa/var/rull: Match VBT with SSFC We want to configure different VBT timings for panels of different sizes and distinguish them through SSFC. We select the reserved bit 6 of SSFC as the flag bit. When using a AUO panel, set this bit to 1. Without splitting, the platform_BootPerf test will fail. BUG=b:379835056 TEST=can match VBT with SSFC -When SSFC is set to 0x40: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 1, use vbt-teliks-auo.bin Change-Id: I413179af0a1346b7d21f17d728d6846c30707978 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/85875/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I413179af0a1346b7d21f17d728d6846c30707978 Gerrit-Change-Number: 85875 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Match VBT with SSFC
by Rui Zhou (Code Review) 07 Jan '25

07 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85875?usp=email ) Change subject: mb/google/nissa/var/rull: Match VBT with SSFC ...................................................................... mb/google/nissa/var/rull: Match VBT with SSFC We want to configure different VBT timings for panels of different sizes and distinguish them through SSFC. We select the reserved bit 6 of SSFC as the flag bit. When using a AUO panel, set this bit to 1. Without splitting, the platform_BootPerf test will fail. BUG=b:379835056 TEST=can match VBT with SSFC -When SSFC is set to 0x40: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 1, use vbt-teliks-auo.bin Change-Id: I413179af0a1346b7d21f17d728d6846c30707978 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/85875/1 diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index 4f8fd47..d98db5f 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -2,6 +2,9 @@ #include <baseboard/variants.h> #include <chip.h> +#include <console/console.h> +#include <drivers/intel/gma/opregion.h> +#include <ec/google/chromeec/ec.h> #include <fw_config.h> #include <sar.h> #include <soc/gpio_soc_defs.h> @@ -41,3 +44,58 @@ graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS, TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS); } + +static int get_ssfc(uint32_t *val) +{ + static uint32_t known_value; + static enum { + SSFC_NOT_READ, + SSFC_AVAILABLE, + } ssfc_state = SSFC_NOT_READ; + + if (ssfc_state == SSFC_AVAILABLE) { + *val = known_value; + return 0; + } + + /* + * If SSFC field is not in the CBI then the value of SSFC will be 0 for + * further processing later since 0 of each bits group means default + * component in a variant. For more detail, please refer to cbi_ssfc.h. + */ + if (google_chromeec_cbi_get_ssfc(&known_value) != 0) { + printk(BIOS_DEBUG, "SSFC not set in CBI\n"); + return -1; + } + + ssfc_state = SSFC_AVAILABLE; + *val = known_value; + printk(BIOS_INFO, "SSFC 0x%x.\n", known_value); + return 0; +} + +const char *mainboard_vbt_filename(void) +{ + uint32_t ssfc; + if (get_ssfc(&ssfc)) { + printk(BIOS_INFO, "Failed to read SSFC, using default vbt-rull.bin\n"); + return "vbt-rull.bin"; + } + + /* + * Determine if the panel is auo based on the SSFC register. + * + * Bit 6 of the SSFC register indicates the panel vendor: + * 0: other pannel + * 1: auo panel + */ + bool is_panel_auo = (ssfc >> 6) & 0x1; + + if (is_panel_auo) { + printk(BIOS_INFO, "Bit 6 of SSFC is 1, use vbt-rull-auo.bin\n"); + return "vbt-rull-auo.bin"; + } + + printk(BIOS_INFO, "Bit 6 of SSFC is 0, use vbt-rull.bin\n"); + return "vbt-rull.bin"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I413179af0a1346b7d21f17d728d6846c30707978 Gerrit-Change-Number: 85875 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the argument type of MT6363
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85839?usp=email ) Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Gerrit-Change-Number: 85839 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 02:34:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025