coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct USB Port Configuration
by Sean Rhodes (Code Review) 31 Jan '25

31 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86238?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct USB Port Configuration ...................................................................... mb/starlabs/starbook/mtl: Correct USB Port Configuration These were initially configured incorrectly; adjust them to match the schematic: * Front USB-C: USB2-1 / TCP0 * Back USB-C: USB2-2 / TCP1 * Left USB-A: USB2-3 / USB3-1 * Right USB-A: USB2-7 / … [View More]USB3-2 * SD Card: USB2-4 * Webcam: USB2-5 * Bluetooth: USB2-10 TEST=boot starbook/mtl, check USB-C and USB-A function, enter/exit S3. Change-Id: I882d70a1d7db0af7ff8e344a3c42a2a9e62df4e8 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86238 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index 86605ec..a138438 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -34,13 +34,13 @@ chip drivers/usb/acpi device ref tcss_root_hub on chip drivers/usb/acpi - register "desc" = ""USB Type-C"" + register "desc" = ""Front USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB Type-C"" + register "desc" = ""Back USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 1)" device ref tcss_usb3_port2 on end @@ -55,11 +55,11 @@ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Motherboard USB 3.0 Type-C Back 7893 mil - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Motherboard USB 3.0 Type-A 8916 mil - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Daughterboard USB 3.0 Type-A 2229 mil @@ -78,22 +78,22 @@ chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB Type-C"" + register "desc" = ""Front USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 0)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB Type-C"" + register "desc" = ""Back USB Type-C"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(0, 1)" - device ref usb2_port3 on end + device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""Left USB Type-A"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(0, 2)" - device ref usb2_port2 on end + device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""Left USB Type-A"" @@ -240,7 +240,7 @@ device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port3 as usb2_port + use usb2_port2 as usb2_port use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I882d70a1d7db0af7ff8e344a3c42a2a9e62df4e8 Gerrit-Change-Number: 86238 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Disconnect PEDET GPIO
by Sean Rhodes (Code Review) 31 Jan '25

31 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86235?usp=email ) Change subject: mb/starlabs/starlite_adl: Disconnect PEDET GPIO ...................................................................... mb/starlabs/starlite_adl: Disconnect PEDET GPIO This GPIO is only used for SATA SSDs so set it as not connected. Change-Id: I42c0ec36eee81a849f744a2d03862797f2463921 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.… [View More]

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[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Disconnect WiFi Sleep GPIO
by Sean Rhodes (Code Review) 31 Jan '25

31 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86236?usp=email ) Change subject: mb/starlabs/starlite_adl: Disconnect WiFi Sleep GPIO ...................................................................... mb/starlabs/starlite_adl: Disconnect WiFi Sleep GPIO The schematic shows that this GPIO is not connected, so set it as not connected. Change-Id: Ia62b76055f839c48fc112ca46d8654db5b331cd9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-… [View More]

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[XS] Change in coreboot[main]: Revert "mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration"
by Sean Rhodes (Code Review) 31 Jan '25

31 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86222?usp=email ) Change subject: Revert "mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration" ...................................................................... Revert "mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration" This reverts commit 64b8f2130c2ac928a40e0ba3208781d0e4ad11db. MODEM_CLKREQ is NF2. Change-Id: I3da0d9873535e9287494f32563bc42ca4d4f9579 Signed-off-by: Sean Rhodes <sean(a)… [View More]

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[XS] Change in coreboot[main]: Revert "mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration"
by Sean Rhodes (Code Review) 31 Jan '25

31 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86221?usp=email ) Change subject: Revert "mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration" ...................................................................... Revert "mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration" This reverts commit 5deea4ca73665457a9439fb2e461bf5a45108ad5. MODEM_CLKREQ is NF2. Change-Id: Iaab736bf3dd859b00b0681d9dbcc6273d8000d63 Signed-off-by: Sean Rhodes <… [View More]

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Nick Kochlowski (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85634?usp=email ) Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... Patch Set 17: (4 comments) File src/drivers/amd/opensil/memmap.c: https://… [View More]review.coreboot.org/c/coreboot/+/85634/comment/9747469b_3ed0c6f8?us… : PS16, Line 18: int > i'd expect this to be an unsigned int. iirc this is implementation defined though. […] Done File src/vendorcode/amd/opensil/genoa_poc/memmap.c: https://review.coreboot.org/c/coreboot/+/85634/comment/5e9aaf75_47115384?us… : PS16, Line 10: int > i'd expect this to be an unsigned int or possibly uint32_t Done https://review.coreboot.org/c/coreboot/+/85634/comment/c1c3fe33_2c395782?us… : PS16, Line 37: for (i = 0; i < ARRAY_SIZE(types); i++) : if (enum_type == types[i].type) : break; : if (i == ARRAY_SIZE(types)) : return "Unknown type"; : return types[i].string; > something for another patch, which is why i mark it as resolved, but this code can be rewritten to m […] Agreed, it's much easier to read this way. I added this change to the new patchset. Is that OK or should I push a separate add-on patch just for this? https://review.coreboot.org/c/coreboot/+/85634/comment/16c007d9_b8e2f127?us… : PS16, Line 51: *hole_info = NULL; > i'd also set n_holes to 0 in the error case just to be sure. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 17 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 31 Jan 2025 18:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> [View Less]

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Nick Kochlowski (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85634?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) … [View More]Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... drivers/amd/opensil/memmap.c: Factor out common memmap code to driver Refactor the vendercode openSIL memory map code and move all common calls that do not require any openSIL headers to the driver. Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/memmap.c M src/drivers/amd/opensil/opensil.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/phoenix/memmap.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/ramstage.c 8 files changed, 120 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85634/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 17 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> [View Less]

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Felix Held (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85634?usp=email ) Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... Patch Set 16: (4 comments) File src/drivers/amd/opensil/memmap.c: https://… [View More]review.coreboot.org/c/coreboot/+/85634/comment/1d5d3b2f_629fa159?us… : PS16, Line 18: int i'd expect this to be an unsigned int. iirc this is implementation defined though. from looking at the uint32_t padding after the type field, i'd expect the type field to be assumed to always be an uint32_t so that the struct has a total size of 3 QWORDs. in coreboot unsigned int and uint32_t are identical, so i'd use uint32_t here File src/vendorcode/amd/opensil/genoa_poc/memmap.c: https://review.coreboot.org/c/coreboot/+/85634/comment/01c755ee_2fadd06d?us… : PS16, Line 10: int i'd expect this to be an unsigned int or possibly uint32_t https://review.coreboot.org/c/coreboot/+/85634/comment/0866af67_04a0b235?us… : PS16, Line 37: for (i = 0; i < ARRAY_SIZE(types); i++) : if (enum_type == types[i].type) : break; : if (i == ARRAY_SIZE(types)) : return "Unknown type"; : return types[i].string; something for another patch, which is why i mark it as resolved, but this code can be rewritten to make it easier to read: for (i = 0; i < ARRAY_SIZE(types); i++) if (enum_type == types[i].type) return types[i].string; return "Unknown type"; https://review.coreboot.org/c/coreboot/+/85634/comment/f635fea7_b838da13?us… : PS16, Line 51: *hole_info = NULL; i'd also set n_holes to 0 in the error case just to be sure. maybe top_of_mem too? -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 16 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 31 Jan 2025 17:04:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No [View Less]

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[M] Change in coreboot[main]: soc/intel/denverton_ns: Remove unused memcpy_s function
by Maximilian Brune (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Elyes Haouas, Julius Werner, Paul Menzel. Maximilian Brune has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86233?usp=email ) Change subject: soc/intel/denverton_ns: Remove unused memcpy_s function ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86233?usp=email To unsubscribe, or for help writing … [View More]

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Angel Pons (Code Review) 31 Jan '25

31 Jan '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, Felix Held. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 4: (2 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/86131/comment/e62b1510_7517687f?us…… [View More]

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coreboot-gerrit January 2025