coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
2094 discussions

[S] Change in coreboot[main]: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Subrata Banik. Hello Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84392?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block rather than checking if GPE1_STS(0) is '0'. BUG:362310295 TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check that FADT table includes GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Without the flag, boot to OS and check that FADT table does not include GPE1. FADT should have: GPE1 Block Address : 0 GPE1 Block Length : 0 GPE1 Base Offset : 0 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 Gerrit-Change-Number: 84392 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
by Yidi Lin (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Knox Chiou, Paul Menzel, Xinxiong Xu, Yang Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186 ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84342/comment/4863c6cd_742cd1ca?us… : PS10, Line 12: dts DTS -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 10 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 07:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
by Yidi Lin (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel. Yidi Lin has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ...................................................................... Patch Set 17: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/6be03bb3_92bf4e15?us… : PS17, Line 23: NOT impact boot time no boot time impact -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 17 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
by Kiwi Liu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Mengqi Zhang, Paul Menzel, Yidi Lin. Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ...................................................................... Patch Set 17: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/c9b88eb7_c056bffd?us… : PS12, Line 14: measure eMMC clock ok > Please mention the boot time impact (or no impact) in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 17 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:50:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
by Kiwi Liu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel, Yidi Lin. Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84298?usp=email to look at the new patch set (#17). Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ...................................................................... soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz Mediatek SoCs start operating at eMMC clock around 3MHz right after power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs under 400kHz. When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and get the division value 128. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/128=3.125MHz. So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz. BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok; NOT impact boot time Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/msdc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 17 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
by Yu-Ping Wu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ...................................................................... Patch Set 16: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/2112a717_31d6b8e4?us… : PS12, Line 14: measure eMMC clock ok > https://partnerissuetracker.corp.google.com/issues/356578805#comment44 […] Please mention the boot time impact (or no impact) in the commit message. File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/84298/comment/dff9d473_baf66172?us… : PS15, Line 432: 400 * 1000 * 1000 > In the eMMC coreboot driver, because it involves some MHz and KHz calculation, in order to make the […] Fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 16 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:43:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Simplify FSP global reset definition
by Werner Zeh (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Paul Menzel, Pranava Y N, Rishika Raj, Ronak Kanabar, Sean Rhodes, Subrata Banik, Tarun. Werner Zeh has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email ) Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/c/coreboot/+/84356/comment/b4f48262_df72b5a6?us… : PS6, Line 400: default 5 > I am not a FSP designer but it seems to be following a simple logic. The type is `EFI_STATUS`. `EFI_STATUS` error codes are encoded as `(MAX_BIT | (a))`. For example, `EFI_INVALID_PARAMETER` being `0x80000002` or `0x8000000000000002` on 32-bit or 64-bit respectively. A similar logic is applied to the OEM Status Code: `(MAX_BIT >> 1 | (a))`. This is actually documented in FSP 2.0 specification section **11.2.2 OEM Status Code** (cf. quote below) so technically this is not new. > > > The range of status code that have the highest bit clear and the next to highest bit set > > are reserved for use by OEMs. > > I am having a hard time understanding why cleaning it up now is getting so much push back. Is there an actual use-case I am breaking that I don't see ? > Jérémy, please do not get it wrong. Nobody is pushing you back here, at least it was not my intention. The code review is there in order to get other's point of view on a change just to improve the code quality. And the comments you received here are just proposing a different way to solve it in order to cover the coreboot use-cases you might not all have in mind. Your work is appreciated, really! > The change I am suggesting (see latest update) is about having a simple Kconfig with the suffix X of `FSP_STATUS_RESET_REQUIRED_X`). `fsp_reset.c` constructs the name of the constant by macro expansion and concatenation (simplified: `FSP_STATUS_RESET_REQUIRED ## FSP_STATUS_GLOBAL_RESET_SUFFIX`) and uses it. File src/soc/intel/common/fsp_reset.c: https://review.coreboot.org/c/coreboot/+/84356/comment/a08dd662_29037de5?us… : PS8, Line 9: #define FSP_STATUS_GLOBAL_RESET \ : (FSP_STATUS_RESET_REQUIRED_COLD + CONFIG_FSP_STATUS_GLOBAL_RESET_INDEX - 1) > There is no "benefits". […] Yes, this is nothing you in person can change. I was not meant to blame *you* for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/84356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Gerrit-Change-Number: 84356 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:42:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>

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[S] Change in coreboot[main]: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
by Yu-Ping Wu (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Knox Chiou, Paul Menzel, Xinxiong Xu, Yang Wu. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186 ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84342/comment/0bdeaf51_c07d4644?us… : PS10, Line 10: kernel can use the corresponding DTS file. To make MT8186T functional on > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 10 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:41:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
by Mengqi Zhang (Code Review) 19 Sep '24

19 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin, Yu-Ping Wu. Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz ...................................................................... Patch Set 16: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/8a10e096_f14a8759?us… : PS12, Line 14: measure eMMC clock ok > gentle ping https://partnerissuetracker.corp.google.com/issues/356578805#comment44 Boot time is here. This change has no impact on boot time. In coreboot stage, emmc just issues two short commands, this result is in line with expectations. -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 16 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 19 Sep 2024 06:17:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/nivviks: Update the power resource for NVM and VCM
by V Sowmya (Code Review) 19 Sep '24

19 Sep '24

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84420?usp=email ) Change subject: mb/google/nissa/var/nivviks: Update the power resource for NVM and VCM ...................................................................... mb/google/nissa/var/nivviks: Update the power resource for NVM and VCM The earlier changes pushed to resolve the camera LED blinking issue led to the regressions with camera autofocus functionality. This change updates the power resource for NVM and VCM to fix the issue. BUG=b:365899407 TEST=Build and boot tivviks. Verified the Autofocus and all the camera sanity tests. Change-Id: Id3e256d59982ac176844e289f18ee450079704b9 Signed-off-by: Sowmya V <v.sowmya(a)intel.com> --- M src/mainboard/google/brya/variants/nivviks/overridetree.cb 1 file changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/84420/1 diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 67c47346..c156d2a 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -437,14 +437,17 @@ # Controls register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X # _ON - register "on_seq.ops_cnt" = "1" + register "on_seq.ops_cnt" = "2" register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" # _OFF - register "off_seq.ops_cnt" = "1" - register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops_cnt" = "2" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 0C on probe WFC WFC_MIPI_OVTI5675 @@ -456,6 +459,19 @@ register "acpi_name" = ""NVM0"" register "chip_name" = ""GT24C08"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "has_power_resource" = "1" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + # Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + + # _ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + # _OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" @@ -509,12 +525,6 @@ register "sdmode_delay" = "5" device generic 0 on end end - chip drivers/sof - register "spkr_tplg" = "max98360a" - register "jack_tplg" = "nau8825" - register "mic_tplg" = "_2ch_pdm0" - device generic 0 on end - end end device ref pcie_rp4 on probe WIFI_CATEGORY WIFI_7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3e256d59982ac176844e289f18ee450079704b9 Gerrit-Change-Number: 84420 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>

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coreboot-gerrit September 2024