coreboot-gerrit September 2024

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[S] Change in coreboot[main]: drivers/efi/capsules.c: fix recording capsule size
by Sergii Dmytruk (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Nico Huber, Sergii Dmytruk. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84542?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: drivers/efi/capsules.c: fix recording capsule size ...................................................................... drivers/efi/capsules.c: fix recording capsule size As mentioned in comments on CB:83422, size of the current data block (which is also the last block of a capsule) was incorrectly used in place of the capsule size: - when publishing a capsule in CBMEM (this worked in practice because CapsuleApp.efi allocates a continuous physical memory) - when aligning target address (which could move output pointer past previously allocated buffer by up to 7 bytes per capsule block) Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/efi/capsules.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84542/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217 Gerrit-Change-Number: 84542 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[S] Change in coreboot[main]: soc/amd/glinda: update the supported MCA banks
by Ana Carolina Cabral (Code Review) 30 Sep '24

30 Sep '24

Ana Carolina Cabral has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84599?usp=email ) Change subject: soc/amd/glinda: update the supported MCA banks ...................................................................... Abandoned https://review.coreboot.org/c/coreboot/+/84374 -- To view, visit https://review.coreboot.org/c/coreboot/+/84599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacab6ec597e830504d7b3c451d567fc402dc8ec3 Gerrit-Change-Number: 84599 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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[S] Change in coreboot[main]: drivers/efi/capsules.c: fix recording capsule size
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Sergii Dmytruk. Nico Huber has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/84542?usp=email ) Change subject: drivers/efi/capsules.c: fix recording capsule size ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84542/comment/b9e9caa4_aeef8578?us… : PS1, Line 8: It's not that obvious what all was wrong before. Please elaborate a little. -- To view, visit https://review.coreboot.org/c/coreboot/+/84542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217 Gerrit-Change-Number: 84542 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 12:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/amd/birman*: I2C slave detection fix
by Ana Carolina Cabral (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84600?usp=email ) Change subject: mb/amd/birman*: I2C slave detection fix ...................................................................... mb/amd/birman*: I2C slave detection fix Change-Id: I24d236c82e6ede2c2311eb1e76499e5a29766133 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman/early_gpio.c M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/birman_plus/early_gpio.c M src/mainboard/amd/birman_plus/gpio.c M src/mainboard/amd/birman_plus/mainboard.c 6 files changed, 87 insertions(+), 307 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84600/1 diff --git a/src/mainboard/amd/birman/early_gpio.c b/src/mainboard/amd/birman/early_gpio.c index 4915996..9e598f0 100644 --- a/src/mainboard/amd/birman/early_gpio.c +++ b/src/mainboard/amd/birman/early_gpio.c @@ -67,9 +67,9 @@ /* I2C2_SDA */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), }; void mainboard_program_early_gpios(void) diff --git a/src/mainboard/amd/birman/gpio.c b/src/mainboard/amd/birman/gpio.c index 74d929d..7519b85 100644 --- a/src/mainboard/amd/birman/gpio.c +++ b/src/mainboard/amd/birman/gpio.c @@ -9,161 +9,54 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* PCIE_SD_WAKE_L */ - PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), - /* UART_WAKE_L_M2_APU */ - PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), - /* MPM_EVENT_L, input or OD output */ - PAD_GPI(GPIO_5, PULL_UP), - /* TPNL_INT_L */ - PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), - /* EC SCI */ - PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW), - /* TPAD_INT_L */ - PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), - /* SD_CARD_PRSNT_L */ - PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ - /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), - /* HP_MIC_DET_L */ - PAD_GPI(GPIO_11, PULL_UP), - /* ALIGN_FLAG_MU_L */ - PAD_GPO(GPIO_12, HIGH), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* WAKE_ON_WAN_L */ - PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), - /* PCIE_WLAN_WAKE_L */ - PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* KBRST_L */ - PAD_NF(GPIO_21, KBRST_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_NONE), - /* PCIE_LOM_WAKE_L */ - PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), - /* GPIO_25: Not available */ - /* PCIE_RST0_L */ - PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), - /* PCIE_RST1_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* GPIO_28: Not available */ /* TPM CS */ PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* INT_CLKREQ_L */ - PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_37: Not available */ - /* CLK_REQ5_L */ - PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE), - /* CLK_REQ6_L */ - PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE), - /* USB2_HDR_P0/1_SMI */ - PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), - /* GPIO_41: Not available */ - /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), - /* GPIO_43 - GPIO_66: Not available */ - /* SPI_ROM_REQ */ - PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), /* ESPI_DATA2 */ PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), /* ESPI_DATA3 */ PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SPI2_CLK */ - PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), - /* GPIO_71 - GPIO_73: Not available */ - /* APU_NFC_DWL_REQ_1V8 */ - PAD_GPO(GPIO_74, LOW), - /* SPI2_CS1_L */ - PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* TPM IRQ */ + PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), /* SPI_ROM_GNT */ PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), - /* ESPI_SOC_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* M2_SSD0_RST_L */ PAD_GPO(GPIO_78, HIGH), /* M2_SSD1_RST_L */ PAD_GPO(GPIO_79, HIGH), - /* ESPI_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* GPIO_82 - GPIO_83: Not available */ - /* FANIN0 */ - PAD_NF(GPIO_84, FANIN0, PULL_NONE), - /* FANOUT0 */ - PAD_NF(GPIO_85, FANOUT0, PULL_NONE), - /* GPIO_86 - GPIO_88: Not available */ - /* I2S CODEC INT */ - PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), - /* ALERT_L_M2_SSD0 */ - PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), - /* NFC IRQ */ - PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW), - /* CLK_REQ0_L */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* GPIO_93 - GPIO_103: Not available */ - /* SPI2_DAT0 */ - PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), - /* SPI2_DAT1 */ - PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), - /* SPI2_DAT2 */ - PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), - /* SPI2_DAT3 */ - PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), - /* GPIO_108 - GPIO_112: Not available */ - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* GPIO_117 - GPIO_129: Not available */ - /* TPM IRQ */ - PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* CLK_REQ3_L */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* CLK_REQ4_L */ - PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), - /* GPIO_133 - GPIO_134: Not available */ - /* UART2_CTS_L */ - PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + + /* Enable UART 2 */ /* UART2_RXD */ PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), - /* UART2_RTS_L */ - PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), /* UART2_TXD */ PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), - /* M2_SSD2_RST_L */ - PAD_GPO(GPIO_139, HIGH), - /* UART0_CTS_L */ - PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART0_RTS_L */ - PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), /* UART0_TXD */ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* M2_SSD3_RST_L */ - PAD_GPO(GPIO_144, HIGH), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* I2C0 SCL */ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), /* I2C0 SDA */ @@ -172,17 +65,14 @@ PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), /* I2C1 SDA */ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* GPIO_149 - GPIO_152: Not available */ - /* UART4_CTS_L */ - PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE), - /* UART4_RTS_L */ - PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE), - /* UART4_RXD */ - PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), - /* UART4_TXD */ - PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), - /* M2_SSD4_RST_L */ - PAD_GPO(GPIO_157, HIGH), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), }; void mainboard_program_gpios(void) diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index f2d3ef9..80731a6 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -35,14 +35,14 @@ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIO, 11, 11 }, - { PIRQ_I2C0, 10, 10 }, - { PIRQ_I2C1, 7, 7 }, - { PIRQ_I2C2, 6, 6 }, - { PIRQ_I2C3, 5, 5 }, - { PIRQ_UART0, 4, 4 }, - { PIRQ_UART1, 3, 3 }, - + { PIRQ_GPIO, 0x7, 0x7 }, + { PIRQ_I2C0, 0xa, 0xa }, + { PIRQ_I2C1, 0xb, 0xb }, + { PIRQ_I2C2, 0x4, 0x4 }, + { PIRQ_I2C3, 0x6, 0x6 }, + { PIRQ_UART0, 0x3, 0x3}, + { PIRQ_UART1, 0xe, 0xe }, + /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, { PIRQ_MISC0, 0x91, 0x00 }, diff --git a/src/mainboard/amd/birman_plus/early_gpio.c b/src/mainboard/amd/birman_plus/early_gpio.c index 4915996..9e598f0 100644 --- a/src/mainboard/amd/birman_plus/early_gpio.c +++ b/src/mainboard/amd/birman_plus/early_gpio.c @@ -67,9 +67,9 @@ /* I2C2_SDA */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), }; void mainboard_program_early_gpios(void) diff --git a/src/mainboard/amd/birman_plus/gpio.c b/src/mainboard/amd/birman_plus/gpio.c index 74d929d..7519b85 100644 --- a/src/mainboard/amd/birman_plus/gpio.c +++ b/src/mainboard/amd/birman_plus/gpio.c @@ -9,161 +9,54 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* PCIE_SD_WAKE_L */ - PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), - /* UART_WAKE_L_M2_APU */ - PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), - /* MPM_EVENT_L, input or OD output */ - PAD_GPI(GPIO_5, PULL_UP), - /* TPNL_INT_L */ - PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), - /* EC SCI */ - PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW), - /* TPAD_INT_L */ - PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), - /* SD_CARD_PRSNT_L */ - PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ - /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), - /* HP_MIC_DET_L */ - PAD_GPI(GPIO_11, PULL_UP), - /* ALIGN_FLAG_MU_L */ - PAD_GPO(GPIO_12, HIGH), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* WAKE_ON_WAN_L */ - PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), - /* PCIE_WLAN_WAKE_L */ - PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* KBRST_L */ - PAD_NF(GPIO_21, KBRST_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_NONE), - /* PCIE_LOM_WAKE_L */ - PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), - /* GPIO_25: Not available */ - /* PCIE_RST0_L */ - PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), - /* PCIE_RST1_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* GPIO_28: Not available */ /* TPM CS */ PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* INT_CLKREQ_L */ - PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_37: Not available */ - /* CLK_REQ5_L */ - PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE), - /* CLK_REQ6_L */ - PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE), - /* USB2_HDR_P0/1_SMI */ - PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), - /* GPIO_41: Not available */ - /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), - /* GPIO_43 - GPIO_66: Not available */ - /* SPI_ROM_REQ */ - PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), /* ESPI_DATA2 */ PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), /* ESPI_DATA3 */ PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SPI2_CLK */ - PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), - /* GPIO_71 - GPIO_73: Not available */ - /* APU_NFC_DWL_REQ_1V8 */ - PAD_GPO(GPIO_74, LOW), - /* SPI2_CS1_L */ - PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* TPM IRQ */ + PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), /* SPI_ROM_GNT */ PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), - /* ESPI_SOC_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* M2_SSD0_RST_L */ PAD_GPO(GPIO_78, HIGH), /* M2_SSD1_RST_L */ PAD_GPO(GPIO_79, HIGH), - /* ESPI_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* GPIO_82 - GPIO_83: Not available */ - /* FANIN0 */ - PAD_NF(GPIO_84, FANIN0, PULL_NONE), - /* FANOUT0 */ - PAD_NF(GPIO_85, FANOUT0, PULL_NONE), - /* GPIO_86 - GPIO_88: Not available */ - /* I2S CODEC INT */ - PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), - /* ALERT_L_M2_SSD0 */ - PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), - /* NFC IRQ */ - PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW), - /* CLK_REQ0_L */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* GPIO_93 - GPIO_103: Not available */ - /* SPI2_DAT0 */ - PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), - /* SPI2_DAT1 */ - PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), - /* SPI2_DAT2 */ - PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), - /* SPI2_DAT3 */ - PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), - /* GPIO_108 - GPIO_112: Not available */ - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* GPIO_117 - GPIO_129: Not available */ - /* TPM IRQ */ - PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* CLK_REQ3_L */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* CLK_REQ4_L */ - PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), - /* GPIO_133 - GPIO_134: Not available */ - /* UART2_CTS_L */ - PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + + /* Enable UART 2 */ /* UART2_RXD */ PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), - /* UART2_RTS_L */ - PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), /* UART2_TXD */ PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), - /* M2_SSD2_RST_L */ - PAD_GPO(GPIO_139, HIGH), - /* UART0_CTS_L */ - PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART0_RTS_L */ - PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), /* UART0_TXD */ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* M2_SSD3_RST_L */ - PAD_GPO(GPIO_144, HIGH), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* I2C0 SCL */ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), /* I2C0 SDA */ @@ -172,17 +65,14 @@ PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), /* I2C1 SDA */ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* GPIO_149 - GPIO_152: Not available */ - /* UART4_CTS_L */ - PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE), - /* UART4_RTS_L */ - PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE), - /* UART4_RXD */ - PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), - /* UART4_TXD */ - PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), - /* M2_SSD4_RST_L */ - PAD_GPO(GPIO_157, HIGH), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), }; void mainboard_program_gpios(void) diff --git a/src/mainboard/amd/birman_plus/mainboard.c b/src/mainboard/amd/birman_plus/mainboard.c index 1e5bc2f..2f2b75a 100644 --- a/src/mainboard/amd/birman_plus/mainboard.c +++ b/src/mainboard/amd/birman_plus/mainboard.c @@ -34,13 +34,13 @@ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIO, 11, 11 }, - { PIRQ_I2C0, 10, 10 }, - { PIRQ_I2C1, 7, 7 }, - { PIRQ_I2C2, 6, 6 }, - { PIRQ_I2C3, 5, 5 }, - { PIRQ_UART0, 4, 4 }, - { PIRQ_UART1, 3, 3 }, + { PIRQ_GPIO, 0x7, 0x7 }, + { PIRQ_I2C0, 0xa, 0xa }, + { PIRQ_I2C1, 0xb, 0xb }, + { PIRQ_I2C2, 0x4, 0x4 }, + { PIRQ_I2C3, 0x6, 0x6 }, + { PIRQ_UART0, 0x3, 0x3}, + { PIRQ_UART1, 0xe, 0xe }, /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/84600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24d236c82e6ede2c2311eb1e76499e5a29766133 Gerrit-Change-Number: 84600 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/glinda: update the supported MCA banks
by Ana Carolina Cabral (Code Review) 30 Sep '24

30 Sep '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84599?usp=email ) Change subject: soc/amd/glinda: update the supported MCA banks ...................................................................... soc/amd/glinda: update the supported MCA banks Change-Id: Iacab6ec597e830504d7b3c451d567fc402dc8ec3 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/soc/amd/glinda/mca.c 1 file changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84599/1 diff --git a/src/soc/amd/glinda/mca.c b/src/soc/amd/glinda/mca.c index c843f4e..300db05 100644 --- a/src/soc/amd/glinda/mca.c +++ b/src/soc/amd/glinda/mca.c @@ -18,12 +18,27 @@ [8] = "L3 cache unit", [9] = "L3 cache unit", [10] = "L3 cache unit", - [11] = "UMC", - [12] = "UMC", - [13] = "CS", - [14] = "CS", - [15] = "NBIO", - [16] = "PIE", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "UMC", + [16] = "UMC", + [17] = "UMC", + [18] = "UMC", + [19] = "CS", + [20] = "CS", + [21] = "CS", + [22] = "CS", + [23] = "", + [24] = "", + [25] = "", + [26] = "", + [27] = "PIE", + [28] = "NBIO", + [29] = "KPX_SERDES", + [30] = "KPX_SERDES", + [31] = "", }; bool mca_has_expected_bank_count(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/84599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacab6ec597e830504d7b3c451d567fc402dc8ec3 Gerrit-Change-Number: 84599 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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[S] Change in coreboot[main]: drivers/efi/capsules.c: check for overflows
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Sergii Dmytruk. Nico Huber has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/84541?usp=email ) Change subject: drivers/efi/capsules.c: check for overflows ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Patchset: PS1: Looks good, commit message could be more elaborate, but doesn't have to be. Sorry for the delay btw. I didn't find the time last week and rather waited for a focused moment. File src/drivers/efi/capsules.c: https://review.coreboot.org/c/coreboot/+/84541/comment/8005afcf_84e724f0?us… : PS1, Line 349: if (capsule_size == 0) { Didn't see that, nice find! -- To view, visit https://review.coreboot.org/c/coreboot/+/84541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43d17d77197fc2cbd721d47941101551603c352a Gerrit-Change-Number: 84541 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 12:02:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: @gaumless@gmail.com why the -1? this brings glinda in line with phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 11:26:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mainboard/intel/beechnutcity_crb: Update full IIO configuration
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84319?usp=email ) Change subject: mainboard/intel/beechnutcity_crb: Update full IIO configuration ...................................................................... mainboard/intel/beechnutcity_crb: Update full IIO configuration Change-Id: I7f4f5406df8ff82b8d3052ff0f370c280967affd Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84319 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/beechnutcity_crb/config/iio.c 1 file changed, 35 insertions(+), 3 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/beechnutcity_crb/config/iio.c b/src/mainboard/intel/beechnutcity_crb/config/iio.c index 117d604..22c36e1 100644 --- a/src/mainboard/intel/beechnutcity_crb/config/iio.c +++ b/src/mainboard/intel/beechnutcity_crb/config/iio.c @@ -3,23 +3,55 @@ #include <soc/iio.h> static const struct iio_pe_config iio_config_table[] = { + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + }}, + /* * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated * then port settings are listed accordingly. The minimal port elements are x2. * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be * disabled. */ - {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + {_IIO_PE_CFG_STRUCT(0x0, PE1, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ - _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2), _IIO_PORT_CFG_STRUCT_DISABLED, _IIO_PORT_CFG_STRUCT_DISABLED, _IIO_PORT_CFG_STRUCT_DISABLED, - _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x6), }}, + + _IIO_PE_CFG_DISABLED(0x0, PE2), + _IIO_PE_CFG_DISABLED(0x0, PE3), + _IIO_PE_CFG_DISABLED(0x0, PE4), + _IIO_PE_CFG_DISABLED(0x0, PE5), + _IIO_PE_CFG_DISABLED(0x0, PEa), + _IIO_PE_CFG_DISABLED(0x0, PEb), + _IIO_PE_CFG_DISABLED(0x0, PEc), + _IIO_PE_CFG_DISABLED(0x0, PEd), + + _IIO_PE_CFG_DISABLED(0x1, PE0), + _IIO_PE_CFG_DISABLED(0x1, PE1), + _IIO_PE_CFG_DISABLED(0x1, PE2), + _IIO_PE_CFG_DISABLED(0x1, PE3), + _IIO_PE_CFG_DISABLED(0x1, PE4), + _IIO_PE_CFG_DISABLED(0x1, PE5), + _IIO_PE_CFG_DISABLED(0x1, PEa), + _IIO_PE_CFG_DISABLED(0x1, PEb), + _IIO_PE_CFG_DISABLED(0x1, PEc), + _IIO_PE_CFG_DISABLED(0x1, PEd), }; const struct iio_pe_config *get_iio_config_table(int *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/84319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f4f5406df8ff82b8d3052ff0f370c280967affd Gerrit-Change-Number: 84319 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update SCI mapping
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84381?usp=email ) Change subject: soc/amd/glinda: Update SCI mapping ...................................................................... soc/amd/glinda: Update SCI mapping source: PPR #57254 Rev 1.71 Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84381 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/include/soc/pci_devs.h M src/soc/amd/glinda/xhci.c 2 files changed, 27 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index a37d3ee..e85a6e3 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -65,10 +65,6 @@ #define GFX_HDA_FUNC 1 #define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) - #define XHCI1_DEV 0x0 #define XHCI1_FUNC 4 #define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) @@ -89,9 +85,18 @@ #define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) -#define XHCI2_DEV 0x0 -#define XHCI2_FUNC 0 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + /* SMBUS */ #define SMBUS_DEV 0x14 diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index 74e8816..70a0d84 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -25,7 +25,13 @@ .level = SMI_SCI_EDG }, { - .scimap = SMITYPE_XHC2_PME, + .scimap = SMITYPE_XHC3_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, .gpe = GEVENT_31, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG @@ -41,18 +47,20 @@ return CB_ERR_ARG; if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { - if (dev->path.pci.devfn == XHCI0_DEVFN) { - *gpe = xhci_sci_sources[0].gpe; - return CB_SUCCESS; - } else if (dev->path.pci.devfn == XHCI1_DEVFN) { + if (dev->path.pci.devfn == XHCI1_DEVFN) { *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { - if (dev->path.pci.devfn == XHCI2_DEVFN - && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { + if (dev->path.pci.devfn == XHCI0_DEVFN) { + *gpe = xhci_sci_sources[0].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { *gpe = xhci_sci_sources[2].gpe; return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Gerrit-Change-Number: 84381 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/amd/glinda/include/soc/smi.h: Update for glinda
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84383?usp=email ) Change subject: soc/amd/glinda/include/soc/smi.h: Update for glinda ...................................................................... soc/amd/glinda/include/soc/smi.h: Update for glinda It aligns the names in the datasheet with the one in the code. It also removes and adds some. Resource: Document 57254 Chapter 15.3.5 TODO it may very well be that I don't have the full truth, because most of these register just have a different name and some of these names like ESPI seem more recent that for example LPC. Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84383 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/glinda/include/soc/smi.h 1 file changed, 29 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h index e5e7833..f0cab4b 100644 --- a/src/soc/amd/glinda/include/soc/smi.h +++ b/src/soc/amd/glinda/include/soc/smi.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_SMI_H #define AMD_GLINDA_SMI_H @@ -25,13 +23,13 @@ #define SMITYPE_G_GENINT1_L 0 #define SMITYPE_G_GENINT2_L 1 #define SMITYPE_G_AGPIO3 2 -#define SMITYPE_G_ESPI_ALERT_L 3 +#define SMITYPE_G_LPC_PME_L 3 #define SMITYPE_G_AGPIO4 4 -#define SMITYPE_G_BLINK 5 +#define SMITYPE_G_LPC_PD_L 5 #define SMITYPE_G_SPKR 6 #define SMITYPE_G_AGPIO5 7 #define SMITYPE_G_WAKE_L 8 -#define SMITYPE_G_SPI_TPM_CS_L 9 +#define SMITYPE_G_LPC_SMI_L 9 #define SMITYPE_G_AGPIO6 10 #define SMITYPE_G_AGPIO7 11 #define SMITYPE_G_USBOC0_L 12 @@ -39,7 +37,7 @@ #define SMITYPE_G_USBOC2_L 14 #define SMITYPE_G_USBOC3_L 15 #define SMITYPE_G_AGPIO23 16 -#define SMITYPE_G_AGPIO32 17 +#define SMITYPE_G_ESPI_RESET_L 17 #define SMITYPE_G_FANIN0 18 #define SMITYPE_G_SYSRESET_L 19 #define SMITYPE_G_AGPIO40 20 @@ -49,13 +47,13 @@ #define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ | (1 << SMITYPE_G_GENINT2_L) \ | (1 << SMITYPE_G_AGPIO3) \ - | (1 << SMITYPE_G_ESPI_ALERT_L) \ + | (1 << SMITYPE_G_LPC_PME_L) \ | (1 << SMITYPE_G_AGPIO4) \ - | (1 << SMITYPE_G_BLINK) \ + | (1 << SMITYPE_G_LPC_PD_L) \ | (1 << SMITYPE_G_SPKR) \ | (1 << SMITYPE_G_AGPIO5) \ | (1 << SMITYPE_G_WAKE_L) \ - | (1 << SMITYPE_G_SPI_TPM_CS_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ | (1 << SMITYPE_G_AGPIO6) \ | (1 << SMITYPE_G_AGPIO7) \ | (1 << SMITYPE_G_USBOC0_L) \ @@ -63,7 +61,7 @@ | (1 << SMITYPE_G_USBOC2_L) \ | (1 << SMITYPE_G_USBOC3_L) \ | (1 << SMITYPE_G_AGPIO23) \ - | (1 << SMITYPE_G_AGPIO32) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ | (1 << SMITYPE_G_FANIN0) \ | (1 << SMITYPE_G_SYSRESET_L) \ | (1 << SMITYPE_G_AGPIO40) \ @@ -72,18 +70,20 @@ | (1 << SMITYPE_G_AGPIO8)) #define SMITYPE_MP2_WAKE 24 #define SMITYPE_MP2_GPIO0 25 -#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_SYS_EVT_B 26 #define SMITYPE_ESPI_WAKE_PME 27 #define SMITYPE_MP2_GPIO1 28 #define SMITYPE_GPP_PME 29 #define SMITYPE_NB_GPP_HOT_PLUG 30 /* 31 Reserved */ -#define SMITYPE_WAKE_L2 32 -#define SMITYPE_PSP 33 -/* 34,35 Reserved */ +#define SMITYPE_WAKE_L 32 +#define SMITYPE_FAKE_0 33 +#define SMITYPE_PSP SMITYPE_FAKE_0 +#define SMITYPE_FAKE_1 34 +#define SMITYPE_FAKE_2 35 #define SMITYPE_ESPI_SCI_B 36 -#define SMITYPE_CIO_FCH_PME_S5_0 37 -#define SMITYPE_CIO_FCH_PME_S5_1 38 +#define SMITYPE_USB4_0_PME 37 +#define SMITYPE_USB4_1_PME 38 #define SMITYPE_AZPME 39 /* 40 Reserved */ #define SMITYPE_GPIO_CTL 41 @@ -99,28 +99,28 @@ #define SMITYPE_PWRBUTTON_UP 51 #define SMITYPE_PROCHOT 52 #define SMITYPE_APU_HW 53 -#define SMITYPE_NB_SCI 54 -#define SMITYPE_RAS_SERR 55 +#define SMITYPE_APU_SCI 54 +#define SMITYPE_INTERNAL_SERR 55 #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-60 Reserved */ -#define SMITYPE_XHC3_PME 61 -#define SMITYPE_XHC4_PME 62 +#define SMITYPE_DSM_TRIGGER_0 59 +#define SMITYPE_DSM_TRIGGER_1 60 +#define SMITYPE_USB_XHC3_PME_3 61 +#define SMITYPE_USB_XHC3_PME_4 62 +#define SMITYPE_XHC3_PME SMITYPE_USB_XHC3_PME_3 +#define SMITYPE_XHC4_PME SMITYPE_USB_XHC3_PME_4 #define SMITYPE_CUR_TEMP_STATUS_5 63 #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -/* 67 Reserved */ -#define SMITYPE_NB_GPP_PME_PULSE 68 -#define SMITYPE_NB_GPP_HP_PULSE 69 -/* 70-71 Reserved */ +/* 67-71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 #define SMITYPE_PWRBUTTON_DOWN 74 #define SMITYPE_SMI_CMD_PORT 75 #define SMITYPE_USB_SMI 76 -#define SMITYPE_SERIRQ 77 +#define SMITYPE_SERIAL_IRQ 77 #define SMITYPE_SMBUS0_INTR 78 /* 79-80 Reserved */ #define SMITYPE_INTRUDER 81 @@ -136,7 +136,7 @@ #define SMITYPE_SHORT_TIMER 142 #define SMITYPE_LONG_TIMER 143 #define SMITYPE_AB_SMI 144 -#define SMITYPE_ANY_RESET 145 +/* 145 Reserved */ #define SMITYPE_ESPI_SMI 146 /* 147 Reserved */ #define SMITYPE_IOTRAP0 148 @@ -169,7 +169,8 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) +# define SMITRIG0_FAKESTS0 (1 << 25) +# define SMITRIG0_PSP SMITRIG0_FAKESTS0 # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) -- To view, visit https://review.coreboot.org/c/coreboot/+/84383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Gerrit-Change-Number: 84383 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Cabral

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coreboot-gerrit September 2024