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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
2 files changed, 27 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/6
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Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84342/comment/4863c6cd_742cd1ca?us… :
PS10, Line 12: dts
DTS
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Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/6be03bb3_92bf4e15?us… :
PS17, Line 23: NOT impact boot time
no boot time impact
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Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/c9b88eb7_c056bffd?us… :
PS12, Line 14: measure eMMC clock ok
> Please mention the boot time impact (or no impact) in the commit message.
Done
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Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; NOT impact boot time
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/17
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Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
Patch Set 16: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/2112a717_31d6b8e4?us… :
PS12, Line 14: measure eMMC clock ok
> https://partnerissuetracker.corp.google.com/issues/356578805#comment44 […]
Please mention the boot time impact (or no impact) in the commit message.
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/dff9d473_baf66172?us… :
PS15, Line 432: 400 * 1000 * 1000
> In the eMMC coreboot driver, because it involves some MHz and KHz calculation, in order to make the […]
Fine.
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Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
......................................................................
Patch Set 11:
(2 comments)
File src/soc/intel/apollolake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84356/comment/b4f48262_df72b5a6?us… :
PS6, Line 400: default 5
> I am not a FSP designer but it seems to be following a simple logic. The type is `EFI_STATUS`. `EFI_STATUS` error codes are encoded as `(MAX_BIT | (a))`. For example, `EFI_INVALID_PARAMETER` being `0x80000002` or `0x8000000000000002` on 32-bit or 64-bit respectively. A similar logic is applied to the OEM Status Code: `(MAX_BIT >> 1 | (a))`. This is actually documented in FSP 2.0 specification section **11.2.2 OEM Status Code** (cf. quote below) so technically this is not new.
>
> > The range of status code that have the highest bit clear and the next to highest bit set
> > are reserved for use by OEMs.
>
> I am having a hard time understanding why cleaning it up now is getting so much push back. Is there an actual use-case I am breaking that I don't see ?
>
Jérémy, please do not get it wrong. Nobody is pushing you back here, at least it was not my intention. The code review is there in order to get other's point of view on a change just to improve the code quality. And the comments you received here are just proposing a different way to solve it in order to cover the coreboot use-cases you might not all have in mind. Your work is appreciated, really!
> The change I am suggesting (see latest update) is about having a simple Kconfig with the suffix X of `FSP_STATUS_RESET_REQUIRED_X`). `fsp_reset.c` constructs the name of the constant by macro expansion and concatenation (simplified: `FSP_STATUS_RESET_REQUIRED ## FSP_STATUS_GLOBAL_RESET_SUFFIX`) and uses it.
File src/soc/intel/common/fsp_reset.c:
https://review.coreboot.org/c/coreboot/+/84356/comment/a08dd662_29037de5?us… :
PS8, Line 9: #define FSP_STATUS_GLOBAL_RESET \
: (FSP_STATUS_RESET_REQUIRED_COLD + CONFIG_FSP_STATUS_GLOBAL_RESET_INDEX - 1)
> There is no "benefits". […]
Yes, this is nothing you in person can change. I was not meant to blame *you* for this.
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Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 10: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84342/comment/0bdeaf51_c07d4644?us… :
PS10, Line 10: kernel can use the corresponding DTS file. To make MT8186T functional on
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
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Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/8a10e096_f14a8759?us… :
PS12, Line 14: measure eMMC clock ok
> gentle ping
https://partnerissuetracker.corp.google.com/issues/356578805#comment44
Boot time is here. This change has no impact on boot time. In coreboot stage, emmc just issues two short commands, this result is in line with expectations.
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Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>