Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84410?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Add GPE1 support in pmutil.c
......................................................................
soc/intel/ptl: Add GPE1 support in pmutil.c
This change is to add the required GPE1 override functions for PTL.
The override functions are called in Intel common pmclib.c. NOTE that
GPE1 bits are SOC-specific and they are related to GPE0 events.
1. When CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is set, the SOC
GPE1 override functions soc_pmc_disable_std_gpe1() and
soc_pmc_enable_std_gpe1() are required in order to configure GPE1 bits
properly according to the corresponding GPE0 bits.
2. The mapping for GPE1 bits to their readable string is also provided
BUG=b:362310295
TEST=This cannot be tested directly. Build with
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 in google/fatcat or
inte/ptlrvp. Boot to OS, Check both GPE0 and GPE1 EN bits.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Ia79c49d399eff4b2f6978323b2f5e2bb167d8638
---
M src/soc/intel/pantherlake/pmutil.c
1 file changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/84410/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/84410?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia79c49d399eff4b2f6978323b2f5e2bb167d8638
Gerrit-Change-Number: 84410
Gerrit-PatchSet: 3
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )
Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................
Patch Set 13:
(2 comments)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/e1de00ff_7496cd2e?us… :
PS12, Line 153: all
> `All` and same for all below comments as well
Done
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/aa46e299_a37e6d91?us… :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> > > Subrata, we will hit the GPE1_* marco redefined build error if CONFIG_SOC_INTEL_COMMON_BLOCK_ACP […]
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
Gerrit-Change-Number: 84297
Gerrit-PatchSet: 13
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Gerrit-Comment-Date: Thu, 19 Sep 2024 07:48:37 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com>
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Attention is currently required from: Cliff Huang, Kapil Porwal, Paul Menzel, Pranava Y N.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84297?usp=email
to look at the new patch set (#13).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................
soc/intel/ptl: Define GPE1 macros and register fields
New GPE1 bits are introduced in PTL for internal devices, incuding
PME_B0, hot plug, and PCIe events.
defines for GPE number for additional STD GPE0 in PTL
defines for GPE number for GPE1
defines for GPE1 bits
NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits.
BUG=362310295
TEST=This cannot be tested directly.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
---
M src/soc/intel/pantherlake/include/soc/gpe.h
M src/soc/intel/pantherlake/include/soc/pm.h
2 files changed, 438 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/13
--
To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
Gerrit-Change-Number: 84297
Gerrit-PatchSet: 13
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: Hung-Te Lin, Mengqi Zhang, Paul Menzel, Yidi Lin.
Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
Patch Set 18: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/7df63925_43db3f7f?us… :
PS17, Line 23: NOT impact boot time
> no boot time impact
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 18
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Comment-Date: Thu, 19 Sep 2024 07:46:45 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>
Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel.
Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84298?usp=email
to look at the new patch set (#18).
Change subject: soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
......................................................................
soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; no boot time impact
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/18
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 18
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Attention is currently required from: Knox Chiou, Paul Menzel, Xinxiong Xu, Yang Wu.
Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email )
Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 11: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Gerrit-Change-Number: 84342
Gerrit-PatchSet: 11
Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
Gerrit-Comment-Date: Thu, 19 Sep 2024 07:40:55 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 28:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/8db0fda5_f797b4bc?us… :
PS27, Line 235: const char *const *soc_std_gpe1_sts_array(int idx, size_t *a);
> u can also move this inside `#if` and keep a inline `NULL` API when `!SOC_INTEL_COMMON_BLOCK_ACPI_HA […]
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/320c9b05_0fb3cd52?us… :
PS27, Line 237: HAVE
> > shoudn't we need to clear and disable GPE1 events regardless we use GPE1 or not. […]
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
Gerrit-Change-Number: 84104
Gerrit-PatchSet: 28
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Thu, 19 Sep 2024 07:35:49 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com>
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu, Paul Menzel.
Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#28).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 flags.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=b:362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 flags, boot google/fatcat
or intel/ptlrvp DUT, and check if GPE1 sts bits have been printed
during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 123 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/28
--
To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
Gerrit-Change-Number: 84104
Gerrit-PatchSet: 28
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Attention is currently required from: Knox Chiou, Paul Menzel, Xinxiong Xu, Yidi Lin.
Yang Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email )
Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84342/comment/46747e5a_77185f91?us… :
PS10, Line 10: kernel can use the corresponding DTS file. To make MT8186T functional on
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]
Done
https://review.coreboot.org/c/coreboot/+/84342/comment/5ddcf973_a5c89d9b?us… :
PS10, Line 12: dts
> DTS
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Gerrit-Change-Number: 84342
Gerrit-PatchSet: 11
Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Comment-Date: Thu, 19 Sep 2024 07:29:21 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>
Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>
Attention is currently required from: Knox Chiou, Paul Menzel, Xinxiong Xu, Yang Wu.
Hello Hung-Te Lin, Knox Chiou, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84342?usp=email
to look at the new patch set (#11).
Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and
kernel can use the corresponding DTS file. To make MT8186T functional
on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the
correct DTS file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffeff.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/boardid.c
1 file changed, 13 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84342/11
--
To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Gerrit-Change-Number: 84342
Gerrit-PatchSet: 11
Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com>
Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>