September 2024 - coreboot-gerrit

[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Martin L Roth (Code Review) Sept. 30, 2024

Sept. 30, 2024

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... soc/amd/glinda: Update gpp bridge naming scheme This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/soc/amd/glinda/chipset.cb 3 files changed, 15 insertions(+), 12 deletions(-) Approvals: Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index f1a99f6..2e06f2b 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -158,9 +158,10 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 1df02ed..e867f01 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 6e23c2d..f328797 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -14,13 +14,15 @@ device pci 01.2 alias usb4_pcie_bridge_1 off end device pci 01.3 alias usb4_pcie_bridge_2 off end + # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy device function, do not disable device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Martin L Roth (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Maximilian Brune. Martin L Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... Patch Set 3: -Verified (1 comment) Patchset: PS3: Sorry, that was just a verified -1. Didn't realize it'd stick after jenkins came back online. -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:50:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads
by Karthik Ramasubramanian (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Ren Kuo. Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84545?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84545/comment/5c54b23c_b950a6d6?us… : PS4, Line 8: : In previous cl:84124 Previously in CB:84124 https://review.coreboot.org/c/coreboot/+/84545/comment/a946eb29_ca964314?us… : PS4, Line 10: , and fp_disable_pads need to be updated. . Hence update fp_disable_pads configuration to include that GPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/84545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Gerrit-Change-Number: 84545 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cnvi: Add SBTE Method
by Sean Rhodes (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83714?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cnvi: Add SBTE Method ...................................................................... soc/intel/cnvi: Add SBTE Method Add Set Bluetooth Enable method which controls the Tx state of the BTEN vGPIO. Change-Id: I11cdf654223daa7b417d6aa18855b48b50a8faa4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/Kconfig M src/soc/intel/common/block/cnvi/cnvi.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83714/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/83714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11cdf654223daa7b417d6aa18855b48b50a8faa4 Gerrit-Change-Number: 83714 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/intel/cnvi: Add GBTE Method
by Sean Rhodes (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83715?usp=email to look at the new patch set (#13). Change subject: soc/intel/cnvi: Add GBTE Method ...................................................................... soc/intel/cnvi: Add GBTE Method Add Get Bluetooth Enable method which gets the Tx state of the BTEN vGPIO. Change-Id: I8f6b97b0961579f36cd053b0252213c3335b1c62 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83715/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/83715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f6b97b0961579f36cd053b0252213c3335b1c62 Gerrit-Change-Number: 83715 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads
by Karthik Ramasubramanian (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Ren Kuo. Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84545?usp=email ) Change subject: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Gerrit-Change-Number: 84545 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:40:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
by Matt DeVillier (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84134?usp=email ) Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84134/comment/02e3d944_83ab58a8?us… : PS16, Line 499: s_cfg this and instance below should be `params->` not `s_cfg->` -- To view, visit https://review.coreboot.org/c/coreboot/+/84134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Gerrit-Change-Number: 84134 Gerrit-PatchSet: 16 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:37:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cnvi: Add power related methods
by Matt DeVillier (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83711?usp=email ) Change subject: soc/intel/cnvi: Add power related methods ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39 Gerrit-Change-Number: 83711 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:28:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cnvi: Add GBTE Method
by Matt DeVillier (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83715?usp=email ) Change subject: soc/intel/cnvi: Add GBTE Method ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/common/block/cnvi/cnvi.c: https://review.coreboot.org/c/coreboot/+/83715/comment/57d8c7d2_bf0e1844?us… : PS5, Line 300: 0x090a0000 > Address of VGPIO_0 add as a comment above? -- To view, visit https://review.coreboot.org/c/coreboot/+/83715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f6b97b0961579f36cd053b0252213c3335b1c62 Gerrit-Change-Number: 83715 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:28:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XL] Change in coreboot[main]: mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant
by Matt DeVillier (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/74445?usp=email ) Change subject: mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737 Gerrit-Change-Number: 74445 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:27:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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