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Change subject: drivers/aspeed/common: Add AST2600 support
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
File src/drivers/aspeed/common/ast_main.c:
https://review.coreboot.org/c/coreboot/+/84425/comment/8cabccb9_3a7860b1?us… :
PS2, Line 200: AST2500
This change shouldn't matter when adding support for the AST2600
File src/drivers/aspeed/common/ast_mode.c:
https://review.coreboot.org/c/coreboot/+/84425/comment/48391565_783fb7cf?us… :
PS2, Line 295: ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xFC, 0xFD, 0x00);
Does this need to be done on non-AST2600 chips?
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Change subject: soc/amd/glinda/chipset.cb: Update for glinda
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/amd/birman/devicetree_glinda.cb:
https://review.coreboot.org/c/coreboot/+/84376/comment/ee6dd7dc_2c258a8b?us… :
PS4, Line 211: device ref usb4_xhci_1_root_hub on
> Yes, but I didn't want to add/remove devices in this patch. […]
oh, right. that approach sounds good to me. just mark this as resolved once you've written and pushed a patch for that; only left it as unresolved so that this doesn't get forgotten
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Change subject: mb/intel/archercity_crb: Enable native graphics init
......................................................................
Abandoned
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Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in
northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529
TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot
to OS and check ACPI PDRC device from the ACPI DSDT table. There should
not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
1 file changed, 4 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 51b0e23..dd176e6 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -291,12 +291,12 @@
* B0:D0:F0:Reg.48h
*/
Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB)
-
+#if DMI_BASE_SIZE
/* DMI BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.68h
*/
Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB)
-
+#endif
/* EP BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.40h
*/
@@ -322,10 +322,10 @@
CreateDwordField (BUF0, MCHB._BAS, MBR0)
MBR0 = \_SB.PCI0.GMHB ()
-
+#if DMI_BASE_SIZE
CreateDwordField (BUF0, DMIB._BAS, DBR0)
DBR0 = \_SB.PCI0.GDMB ()
-
+#endif
CreateDwordField (BUF0, EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.GEPB ()
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Change subject: Documentation/soc/intel/xeon_sp: Update community preview guide
......................................................................
Documentation/soc/intel/xeon_sp: Update community preview guide
Update community preview guide for full Xeon 6 supports.
Change-Id: If0eb6d889e9c1c2ba162a94daeee260d51f48b83
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
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---
M Documentation/soc/intel/xeon_sp/community_preview_guide.md
1 file changed, 42 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84330/7
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Change subject: Documentation/soc/intel/xeon_sp: Update community preview guide
......................................................................
Documentation/soc/intel/xeon_sp: Update community preview guide
Update community preview guide for full Xeon 6 supports.
Change-Id: If0eb6d889e9c1c2ba162a94daeee260d51f48b83
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
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---
M Documentation/soc/intel/xeon_sp/community_preview_guide.md
1 file changed, 41 insertions(+), 36 deletions(-)
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