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Hello Felix Singer, Maxim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
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Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
mb/erying: Add Erying Polestar G613 Pro (TGL-H)
Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E 0x3f8)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports
- M.2 NGFF WiFi
- PCI-E Resizable BAR (ReBAR)
- VT-x
WIP/Broken:
- PCI-E ASPM (also broken on vendor's FW, clocks are messed up)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (seemingly a simple fix)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor hasn't enabled any protections on SPI chip.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com>
---
A src/mainboard/erying/Kconfig
A src/mainboard/erying/Kconfig.name
A src/mainboard/erying/tgl/Kconfig
A src/mainboard/erying/tgl/Kconfig.name
A src/mainboard/erying/tgl/Makefile.mk
A src/mainboard/erying/tgl/board_info.txt
A src/mainboard/erying/tgl/bootblock.c
A src/mainboard/erying/tgl/cmos.layout
A src/mainboard/erying/tgl/data.vbt
A src/mainboard/erying/tgl/devicetree.cb
A src/mainboard/erying/tgl/dsdt.asl
A src/mainboard/erying/tgl/gpio.h
A src/mainboard/erying/tgl/hda_verb.c
A src/mainboard/erying/tgl/ramstage.c
A src/mainboard/erying/tgl/romstage_fsp_params.c
15 files changed, 841 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/9
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Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email )
Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84382/comment/432c7d51_6261628d?us… :
PS2, Line 7: soc/amd/glinda: Update I2C for glinda
> Maybe: […]
That makes it sound like I reviewed the whole soc/amd/glinda code. Maybe if I write:
`src/soc/amd/glinda/include/soc/i2c.h: Review and Update for glinda` ?
https://review.coreboot.org/c/coreboot/+/84382/comment/d4444d43_be650f49?us… :
PS2, Line 9: I24
> I2C4
Done
https://review.coreboot.org/c/coreboot/+/84382/comment/873b2737_1e15221c?us… :
PS2, Line 10:
> Mention that you reviewed the file, so the to-do is removed?
Done
File src/soc/amd/glinda/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/84382/comment/0eed1f7d_ffa1c331?us… :
PS2, Line 117: #define SMITYPE_USB_PD_I2C4_INTR2 70
> same here
Done
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Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84382?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
soc/amd/glinda: Update I2C for glinda
Reviewed i2c.h file and removed the TODO.
I2C4 and I2C5 don't exist so they are removed from the SOC code.
Reference: Document 57254
Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/glinda/include/soc/aoac_defs.h
M src/soc/amd/glinda/include/soc/i2c.h
M src/soc/amd/glinda/include/soc/smi.h
5 files changed, 2 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/3
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Change subject: mb/google/fatcat: Add FW_CONFIG
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84408/comment/5a880016_64ffaee9?us… :
PS1, Line 10: ALC722
ALC272?
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Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84382/comment/c10855fc_b03556b5?us… :
PS2, Line 7: soc/amd/glinda: Update I2C for glinda
Maybe:
soc/amd/glinda: Review and remove non-existing I2C4 and I2C5
https://review.coreboot.org/c/coreboot/+/84382/comment/fe8953f5_69a7ab10?us… :
PS2, Line 9: I24
I2C4
https://review.coreboot.org/c/coreboot/+/84382/comment/965b0f3a_87099e05?us… :
PS2, Line 10:
Mention that you reviewed the file, so the to-do is removed?
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Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84232/comment/9c4b6cf2_8c516b37?us… :
PS4, Line 9: no port
> Our DB has C1 port before, and add DB without C1 port
Thank you. Please amend the message accordingly.
https://review.coreboot.org/c/coreboot/+/84232/comment/17093e2f_c8f629b0?us… :
PS4, Line 14: flash and check boot log on DUT.
> Set fw config to DB_PORTS_LTE and check […]
Thank you. Please amend the message accordingly.
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Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/glinda/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/84382/comment/b4e26230_244f6016?us… :
PS2, Line 117: #define SMITYPE_USB_PD_I2C4_INTR2 70
same here
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83107?usp=email
to look at the new patch set (#22).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
......................................................................
mb/asrock: Add Asrock Industrial IMB-1222 motherboard
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX
motherboard [1].
Working:
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver);
- DP (both), HDMI;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.0 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports;
- onboard speaker;
- HWM/FANs control (fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME with me_cleaner [2];
Payload:
- Linux as payload;
- LinuxBoot;
- SeaBIOS;
- edk2 [3].
Bootable OS:
- Ubuntu 22.04 (Linux 6.5.0-15-generic);
- Ubuntu 24.04 (Linux 6.8.0-41-generic);
- Microsoft Windows 10 Pro 10.0.19045.4780 (22H2 2022).
Unknown/untested:
- USB3.0 in M.2 Key-B 3042/3052 slot;
- eDP/LVDS;
- PCIe riser cards;
- SPDIF.
There is no schematic/boardview, reverse engineering only.
This port is based on system76/bonw14 because it has a similar topology.
[1] https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
[2] XutaxKamay's me_cleaner fork, https://github.com/XutaxKamay/me_cleaner,
v1.2-9-gf20532d
[3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2
uefipayload_2408 branch
Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A Documentation/mainboard/asrock/imb-1222.md
M Documentation/mainboard/index.md
A src/mainboard/asrock/imb-1222/Kconfig
A src/mainboard/asrock/imb-1222/Kconfig.name
A src/mainboard/asrock/imb-1222/Makefile.mk
A src/mainboard/asrock/imb-1222/acpi/mainboard.asl
A src/mainboard/asrock/imb-1222/acpi/sleep.asl
A src/mainboard/asrock/imb-1222/board_info.txt
A src/mainboard/asrock/imb-1222/bootblock.c
A src/mainboard/asrock/imb-1222/cmos.default
A src/mainboard/asrock/imb-1222/cmos.layout
A src/mainboard/asrock/imb-1222/data.vbt
A src/mainboard/asrock/imb-1222/devicetree.cb
A src/mainboard/asrock/imb-1222/dsdt.asl
A src/mainboard/asrock/imb-1222/gma-mainboard.ads
A src/mainboard/asrock/imb-1222/gpio.c
A src/mainboard/asrock/imb-1222/gpio_beep.c
A src/mainboard/asrock/imb-1222/hda_verb.c
A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h
A src/mainboard/asrock/imb-1222/include/mainboard/superio.h
A src/mainboard/asrock/imb-1222/panic.c
A src/mainboard/asrock/imb-1222/ramstage.c
A src/mainboard/asrock/imb-1222/romstage.c
A src/mainboard/asrock/imb-1222/superio.c
24 files changed, 1,318 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/22
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Change subject: mb/google/fatcat: Add FW_CONFIG
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84408/comment/69089484_19560b1f?us… :
PS1, Line 11: MAX9857A
MAX98357A?
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Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email )
Change subject: mb/google/fatcat: Add GPIO settings
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/84405/comment/76fb35b2_4457490a?us… :
PS1, Line 427: /* GPP_A08: X1_PCIE_SLOT_PWR_EN */
: PAD_CFG_GPO(GPP_A08, 0, PLTRST),
:
> Subrata, we don't use fw_config in early and romstage for our PTL and SoCs in the past. Jemery and I was trying to make the changes and we ran into several issues. There are some common code area that needs time to make it clean as well, as well Can we add a TODO list for using early stage fw_config and we can create a proper separate common code change and MB CLs later on?
I have two major questions about the GPIO configuration for fatcat.
1. Do we need all these different HW configurations? I assume the answer is TBD, and we will hear back from our HW team who took AI to get back on the fatcat SKU configuration. This will help us create fw_config.
2. Why do we need to program these GPIOs so early in the boot code, like PWR EN? If we need to meet the power seq diagram, then we need to bring FW config (varaint.c) in bootblock, which I would like to avoid as bootblock is part of RO code.
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