coreboot-gerrit September 2024

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[S] Change in coreboot[main]: soc/amd/glinda: Remove non-exisiting I2C definitions
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions ...................................................................... soc/amd/glinda: Remove non-exisiting I2C definitions Glinda doesn't contain I2C4 and I2C5 like Mendocino it was copied from. Remove their definitions. Reference: Document 57254 Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84382 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/glinda/include/soc/aoac_defs.h M src/soc/amd/glinda/include/soc/i2c.h M src/soc/amd/glinda/include/soc/smi.h 5 files changed, 2 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 2218ce3..8c58f5b 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -65,7 +65,6 @@ { PIRQ_I2C3, "I2C3" }, { PIRQ_UART0, "UART0" }, { PIRQ_UART1, "UART1" }, - { PIRQ_I2C4, "I2C4" }, { PIRQ_UART4, "UART4" }, { PIRQ_UART2, "UART2" }, { PIRQ_UART3, "UART3" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index c7ff65b..ebe1d2c 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -54,7 +54,6 @@ #define PIRQ_I2C3 0x73 /* I2C3 */ #define PIRQ_UART0 0x74 /* UART0 */ #define PIRQ_UART1 0x75 /* UART1 */ -#define PIRQ_I2C4 0x76 /* I2C4 */ #define PIRQ_UART4 0x77 /* UART4 */ #define PIRQ_UART2 0x78 /* UART2 */ #define PIRQ_UART3 0x79 /* UART3 */ diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h index b923ab3..98fb4ce 100644 --- a/src/soc/amd/glinda/include/soc/aoac_defs.h +++ b/src/soc/amd/glinda/include/soc/aoac_defs.h @@ -11,8 +11,6 @@ #define FCH_AOAC_DEV_I2C1 6 #define FCH_AOAC_DEV_I2C2 7 #define FCH_AOAC_DEV_I2C3 8 -#define FCH_AOAC_DEV_I2C4 9 -#define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART2 16 diff --git a/src/soc/amd/glinda/include/soc/i2c.h b/src/soc/amd/glinda/include/soc/i2c.h index f942c3b..05c6350 100644 --- a/src/soc/amd/glinda/include/soc/i2c.h +++ b/src/soc/amd/glinda/include/soc/i2c.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_I2C_H #define AMD_GLINDA_I2C_H diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h index 611840c..e5e7833 100644 --- a/src/soc/amd/glinda/include/soc/smi.h +++ b/src/soc/amd/glinda/include/soc/smi.h @@ -85,7 +85,7 @@ #define SMITYPE_CIO_FCH_PME_S5_0 37 #define SMITYPE_CIO_FCH_PME_S5_1 38 #define SMITYPE_AZPME 39 -#define SMITYPE_USB_PD_I2C4 40 +/* 40 Reserved */ #define SMITYPE_GPIO_CTL 41 #define SMITYPE_XHC2_PME 42 #define SMITYPE_ALT_HPET_ALARM 43 @@ -114,8 +114,7 @@ /* 67 Reserved */ #define SMITYPE_NB_GPP_PME_PULSE 68 #define SMITYPE_NB_GPP_HP_PULSE 69 -#define SMITYPE_USB_PD_I2C4_INTR2 70 -/* 71 Reserved */ +/* 70-71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 #define SMITYPE_PWRBUTTON_DOWN 74 -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/brya/var/bujia: Add Wifi SAR for bujia
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84501?usp=email ) Change subject: mb/google/brya/var/bujia: Add Wifi SAR for bujia ...................................................................... mb/google/brya/var/bujia: Add Wifi SAR for bujia Add wifi sar for bujia. BUG=b:345364452 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6 Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/bujia/Makefile.mk A src/mainboard/google/brya/variants/bujia/variant.c 3 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Eric Lai: Looks good to me, approved Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5f1e6b9..4f49df2 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -187,6 +187,7 @@ config BOARD_GOOGLE_BUJIA select BOARD_GOOGLE_BASEBOARD_BRASK + select CHROMEOS_WIFI_SAR if CHROMEOS select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE diff --git a/src/mainboard/google/brya/variants/bujia/Makefile.mk b/src/mainboard/google/brya/variants/bujia/Makefile.mk index bc39984..175d5bb 100644 --- a/src/mainboard/google/brya/variants/bujia/Makefile.mk +++ b/src/mainboard/google/brya/variants/bujia/Makefile.mk @@ -5,3 +5,4 @@ ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/bujia/variant.c b/src/mainboard/google/brya/variants/bujia/variant.c new file mode 100644 index 0000000..76f0f52 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6 Gerrit-Change-Number: 84501 Gerrit-PatchSet: 4 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/kahlee/var/careena: Make sure bid isn't used uninitialized
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84206?usp=email ) Change subject: mb/google/kahlee/var/careena: Make sure bid isn't used uninitialized ...................................................................... mb/google/kahlee/var/careena: Make sure bid isn't used uninitialized GCC with LTO cought this. Warning: src/mainboard/google/kahlee/variants/careena/variant.c:44:12: error: 'bid' may be used uninitialized [-Werror=maybe-uninitialized] 44 | if (bid == 7) | ^ src/mainboard/google/kahlee/variants/careena/variant.c: In function 'car_stage_entry': src/mainboard/google/kahlee/variants/careena/variant.c:24:18: note: 'bid' was declared here 24 | uint32_t bid; Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84206 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: coreboot org <coreboot.org(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/variants/careena/variant.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: coreboot org: Looks good to me, approved build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index 33ad260..5a393e2 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -38,7 +38,8 @@ } } - google_chromeec_get_board_version(&bid); + if (google_chromeec_get_board_version(&bid)) + return; if (bid == 7) /* -- To view, visit https://review.coreboot.org/c/coreboot/+/84206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d Gerrit-Change-Number: 84206 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: inteltool: elkhartlake: keep the same names as coreboot code uses
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84190?usp=email ) Change subject: inteltool: elkhartlake: keep the same names as coreboot code uses ...................................................................... inteltool: elkhartlake: keep the same names as coreboot code uses coreboot doesn't have a leading zero in gpio < 10. E.g. G00 -> G0 Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84190 Reviewed-by: coreboot org <coreboot.org(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M util/inteltool/gpio_names/elkhartlake.h 1 file changed, 131 insertions(+), 131 deletions(-) Approvals: build bot (Jenkins): Verified coreboot org: Looks good to me, approved Nicholas Sudsgaard: Looks good to me, but someone else must approve diff --git a/util/inteltool/gpio_names/elkhartlake.h b/util/inteltool/gpio_names/elkhartlake.h index 75d65d3..43dc0f7 100644 --- a/util/inteltool/gpio_names/elkhartlake.h +++ b/util/inteltool/gpio_names/elkhartlake.h @@ -8,16 +8,16 @@ /* ----------------------------- Elkhart Lake ----------------------------- */ const char *const elkhartlake_pch_group_a_names[] = { - "GPP_A00", "PSE_GBE0_RGMII_TXD3", "n/a", - "GPP_A01", "PSE_GBE0_RGMII_TXD2", "n/a", - "GPP_A02", "PSE_GBE0_RGMII_TXD1", "n/a", - "GPP_A03", "PSE_GBE0_RGMII_TXD0", "n/a", - "GPP_A04", "PSE_GBE0_RGMII_TXCLK", "n/a", - "GPP_A05", "PSE_GBE0_RGMII_TXCTL", "n/a", - "GPP_A06", "PSE_GBE0_RGMII_RXCLK", "n/a", - "GPP_A07", "PSE_GBE0_RGMII_RXD3", "n/a", - "GPP_A08", "PSE_GBE0_RGMII_RXD2", "n/a", - "GPP_A09", "PSE_GBE0_RGMII_RXD1", "n/a", + "GPP_A0", "PSE_GBE0_RGMII_TXD3", "n/a", + "GPP_A1", "PSE_GBE0_RGMII_TXD2", "n/a", + "GPP_A2", "PSE_GBE0_RGMII_TXD1", "n/a", + "GPP_A3", "PSE_GBE0_RGMII_TXD0", "n/a", + "GPP_A4", "PSE_GBE0_RGMII_TXCLK", "n/a", + "GPP_A5", "PSE_GBE0_RGMII_TXCTL", "n/a", + "GPP_A6", "PSE_GBE0_RGMII_RXCLK", "n/a", + "GPP_A7", "PSE_GBE0_RGMII_RXD3", "n/a", + "GPP_A8", "PSE_GBE0_RGMII_RXD2", "n/a", + "GPP_A9", "PSE_GBE0_RGMII_RXD1", "n/a", "GPP_A10", "PSE_GBE0_RGMII_RXD0", "n/a", "GPP_A11", "PSE_GBE1_RGMII_TXD3", "n/a", "GPP_A12", "PSE_GBE1_RGMII_TXD2", "n/a", @@ -42,16 +42,16 @@ }; const char *const elkhartlake_pch_group_b_names[] = { - "GPP_B00" ,"PMC_CORE_VID0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_B01" ,"PMC_CORE_VID1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_B02" ,"PMC_VRALERT_N", "n/a", "n/a", "ESPI_ALERT2_N", "n/a", "n/a", "n/a", "PSE_TGPIO25", - "GPP_B03" ,"CPU_GP2", "n/a", "n/a", "ESPI_ALERT0_N", "n/a", "n/a", "n/a", "PSE_TGPIO26", - "GPP_B04" ,"CPU_GP3", "n/a", "n/a", "ESPI_ALERT1_N", "n/a", "n/a", "n/a", "PSE_TGPIO27", - "GPP_B05" ,"PSE_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", - "GPP_B06" ,"PSE_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", - "GPP_B07" ,"PSE_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", - "GPP_B08" ,"PSE_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", - "GPP_B09" ,"SIO_I2C5_SDA", "PSE_I2C2_SDA", "n/a", "ESPI_CS3_N", "n/a", "n/a", "n/a", "n/a", + "GPP_B0" ,"PMC_CORE_VID0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B1" ,"PMC_CORE_VID1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B2" ,"PMC_VRALERT_N", "n/a", "n/a", "ESPI_ALERT2_N", "n/a", "n/a", "n/a", "PSE_TGPIO25", + "GPP_B3" ,"CPU_GP2", "n/a", "n/a", "ESPI_ALERT0_N", "n/a", "n/a", "n/a", "PSE_TGPIO26", + "GPP_B4" ,"CPU_GP3", "n/a", "n/a", "ESPI_ALERT1_N", "n/a", "n/a", "n/a", "PSE_TGPIO27", + "GPP_B5" ,"PSE_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", + "GPP_B6" ,"PSE_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", + "GPP_B7" ,"PSE_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", + "GPP_B8" ,"PSE_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", + "GPP_B9" ,"SIO_I2C5_SDA", "PSE_I2C2_SDA", "n/a", "ESPI_CS3_N", "n/a", "n/a", "n/a", "n/a", "GPP_B10" ,"SIO_I2C5_SCL", "PSE_I2C2_SCL", "n/a", "ESPI_ALERT3_N", "n/a", "n/a", "n/a", "n/a", "GPP_B11" ,"PMC_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", "GPP_B12" ,"PMC_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -78,16 +78,16 @@ }; const char *const elkhartlake_pch_group_c_names[] = { - "GPP_C00", "SMB_CLK", "PSE_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO18", - "GPP_C01", "SMB_DATA", "PSE_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO19", - "GPP_C02", "PSE_PWM00", "SMB_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO29", - "GPP_C03", "PSE_GBE0_MDC", "n/a", "PSE_HSUART3_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", - "GPP_C04", "PSE_GBE0_MDIO", "n/a", "PSE_UART3_RTS_N", "PSE_HSUART3_DE", "n/a", "RSVD", "n/a", "n/a", - "GPP_C05", "PSE_PWM01", "n/a", "PSE_UART3_CTS_N", "n/a", "n/a", "SML_ALERT0_N", "n/a", "PSE_TGPIO30", - "GPP_C06", "PSE_GBE1_MDC", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_C07", "PSE_GBE1_MDIO", "n/a", "PSE_HSUART3_RE", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_C08", "PSE_TGPIO04", "DNX_FORCE_RELOAD", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_C09", "PSE_HSUART0_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_C0", "SMB_CLK", "PSE_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO18", + "GPP_C1", "SMB_DATA", "PSE_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO19", + "GPP_C2", "PSE_PWM00", "SMB_ALERT_N", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO29", + "GPP_C3", "PSE_GBE0_MDC", "n/a", "PSE_HSUART3_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", + "GPP_C4", "PSE_GBE0_MDIO", "n/a", "PSE_UART3_RTS_N", "PSE_HSUART3_DE", "n/a", "RSVD", "n/a", "n/a", + "GPP_C5", "PSE_PWM01", "n/a", "PSE_UART3_CTS_N", "n/a", "n/a", "SML_ALERT0_N", "n/a", "PSE_TGPIO30", + "GPP_C6", "PSE_GBE1_MDC", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C7", "PSE_GBE1_MDIO", "n/a", "PSE_HSUART3_RE", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C8", "PSE_TGPIO04", "DNX_FORCE_RELOAD", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_C9", "PSE_HSUART0_EN", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C10", "PSE_TGPIO05", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C11", "PSE_HSUART0_RE", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "GPP_C12", "PSE_UART0_RXD", "n/a", "n/a", "SIO_UART1_RXD", "n/a", "n/a", "n/a", "n/a", @@ -112,16 +112,16 @@ }; const char *const elkhartlake_pch_group_d_names[] = { - "GPP_D00", "PSE_QEPA0", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "PSE_TGPIO32", - "GPP_D01", "PSE_QEPB0", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "PSE_TGPIO33", - "GPP_D02", "PSE_QEPI0", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "PSE_TGPIO34", - "GPP_D03", "PSE_PWM06", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO35", - "GPP_D04", "PSE_PWM02", "n/a", "RSVD", "PSE_SPI1_CS1_N", "n/a", "n/a", "n/a", "PSE_TGPIO36", - "GPP_D05", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D06", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D07", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D08", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_D09", "PSE_SPI0_CS0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CS0_N", "PSE_TGPIO10", + "GPP_D0", "PSE_QEPA0", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "PSE_TGPIO32", + "GPP_D1", "PSE_QEPB0", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "PSE_TGPIO33", + "GPP_D2", "PSE_QEPI0", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "PSE_TGPIO34", + "GPP_D3", "PSE_PWM06", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO35", + "GPP_D4", "PSE_PWM02", "n/a", "RSVD", "PSE_SPI1_CS1_N", "n/a", "n/a", "n/a", "PSE_TGPIO36", + "GPP_D5", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D6", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D7", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D8", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D9", "PSE_SPI0_CS0_N", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CS0_N", "PSE_TGPIO10", "GPP_D10", "PSE_SPI0_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_CLK", "PSE_TGPIO11", "GPP_D11", "PSE_SPI0_MISO", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_MISO", "PSE_TGPIO12", "GPP_D12", "PSE_SPI0_MOSI", "n/a", "n/a", "n/a", "n/a", "n/a", "SIO_SPI2_MOSI", "PSE_TGPIO13", @@ -143,17 +143,17 @@ }; const char *const elkhartlake_pch_group_gpd_names[] = { - "GPD_00", "PMC_BATLOW_N", - "GPD_01", "PMC_ACPRESENT", - "GPD_02", "RSVD", - "GPD_03", "PMC_PWRBTN_N", - "GPD_04", "PMC_SLP_S3_N", - "GPD_05", "PMC_SLP_S4_N", - "GPD_07", "RSVD", - "GPD_08", "PMC_SUSCLK", - "GPD_09", "RSVD", - "GPD_10", "PMC_SLP_S5_N", - "GPD_11", "RSVD", + "GPD0", "PMC_BATLOW_N", + "GPD1", "PMC_ACPRESENT", + "GPD2", "RSVD", + "GPD3", "PMC_PWRBTN_N", + "GPD4", "PMC_SLP_S3_N", + "GPD5", "PMC_SLP_S4_N", + "GPD7", "RSVD", + "GPD8", "PMC_SUSCLK", + "GPD9", "RSVD", + "GPD10", "PMC_SLP_S5_N", + "GPD11", "RSVD", "GPIO_RSVD_8", "n/a", "GPIO_RSVD_9", "n/a", "GPIO_RSVD_10", "n/a", @@ -169,16 +169,16 @@ }; const char *const elkhartlake_pch_group_e_names[] = { - "GPP_E00", "SATA_LED_N", "SATAXPCIE_0", "RSVD", "RSVD", "RSVD", "RSVD", "SATA_0_GP", "n/a", - "GPP_E01", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", - "GPP_E02", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", - "GPP_E03", "DDI1_HPD", "PNL_MISC_DDI1", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP0", "PSE_TGPIO15", - "GPP_E04", "SATA_0_DEVSLP", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM08", "PSE_TGPIO44", - "GPP_E05", "DDI1_DDC_SDA", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM09", "PSE_TGPIO17", - "GPP_E06", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM10", "PSE_TGPIO18", - "GPP_E07", "DDI1_DDC_SCL", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP1", "PSE_TGPIO16", - "GPP_E08", "n/a", "SATA_1_DEVSLP", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "PSE_TGPIO45", - "GPP_E09", "USB2_OC0_N", "n/a", "RSVD", "RSVD", "n/a", "RSVD", "n/a", "n/a", + "GPP_E0", "SATA_LED_N", "SATAXPCIE_0", "RSVD", "RSVD", "RSVD", "RSVD", "SATA_0_GP", "n/a", + "GPP_E1", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", + "GPP_E2", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", + "GPP_E3", "DDI1_HPD", "PNL_MISC_DDI1", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP0", "PSE_TGPIO15", + "GPP_E4", "SATA_0_DEVSLP", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM08", "PSE_TGPIO44", + "GPP_E5", "DDI1_DDC_SDA", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM09", "PSE_TGPIO17", + "GPP_E6", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "RSVD", "PSE_PWM10", "PSE_TGPIO18", + "GPP_E7", "DDI1_DDC_SCL", "n/a", "RSVD", "RSVD", "RSVD", "RSVD", "CPU_GP1", "PSE_TGPIO16", + "GPP_E8", "n/a", "SATA_1_DEVSLP", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "PSE_TGPIO45", + "GPP_E9", "USB2_OC0_N", "n/a", "RSVD", "RSVD", "n/a", "RSVD", "n/a", "n/a", "GPP_E10", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD" , "n/a", "GPP_E11", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "n/a", "GPP_E12", "n/a", "RSVD", "RSVD", "RSVD", "n/a", "RSVD", "RSVD", "n/a", @@ -203,16 +203,16 @@ }; const char *const elkhartlake_pch_group_f_names[] = { - "GPP_F00", "RSVD", "SIO_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F01", "RSVD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F02", "RSVD", "SIO_UART0_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F03", "RSVD", "SIO_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F04", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_F05", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO14", - "GPP_F06", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO47", - "GPP_F07", "PSE_I2S1_SCLK", "n/a", "n/a", "n/a", "AVS_I2S4_SCLK", "n/a", "n/a", "PSE_TGPIO14", - "GPP_F08", "AVS_I2S_MCLK2", "n/a", "n/a", "PSE_TRACEDATA_0", "ISI_TRACEDATA_0", "n/a", "n/a", "PSE_TGPIO48", - "GPP_F09", "BOOT_PWR_EN", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F0", "RSVD", "SIO_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F1", "RSVD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F2", "RSVD", "SIO_UART0_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F3", "RSVD", "SIO_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F4", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F5", "RSVD", "RSVD", "RSVD", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO14", + "GPP_F6", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO47", + "GPP_F7", "PSE_I2S1_SCLK", "n/a", "n/a", "n/a", "AVS_I2S4_SCLK", "n/a", "n/a", "PSE_TGPIO14", + "GPP_F8", "AVS_I2S_MCLK2", "n/a", "n/a", "PSE_TRACEDATA_0", "ISI_TRACEDATA_0", "n/a", "n/a", "PSE_TGPIO48", + "GPP_F9", "BOOT_PWR_EN", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_F10", "PSE_I2S1_SFRM", "n/a", "n/a", "n/a", "AVS_I2S4_SFRM", "n/a", "n/a", "PSE_TGPIO15", "GPP_F11", "n/a", "n/a", "RSVD", "PSE_TRACECLK", "ISI_TRACECLK", "n/a", "n/a", "PSE_TGPIO49", "GPP_F12", "RSVD", "AVS_I2S4_TXD", "RSVD", "PSE_TRACESWO", "ISI_TRACESWO", "n/a", "n/a", "n/a", @@ -244,16 +244,16 @@ }; const char *const elkhartlake_pch_group_g_names[] = { - "GPP_G00", "SD_SDIO_CMD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G01", "SD_SDIO_D0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G02", "SD_SDIO_D1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G03", "SD_SDIO_D2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G04", "SD_SDIO_D3", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G05", "SD_SDIO_CD_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G06", "SD_SDIO_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_G07", "AVS_I2S2_SCLK", "n/a", "n/a", "DMIC_CLK_A0", "n/a", "n/a", "n/a", "n/a", - "GPP_G08", "AVS_I2S2_SFRM", "RSVD", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "n/a", - "GPP_G09", "AVS_I2S2_TXD", "RSVD", "RSVD", "DMIC_CLK_A1", "n/a", "n/a", "n/a", "n/a", + "GPP_G0", "SD_SDIO_CMD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G1", "SD_SDIO_D0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G2", "SD_SDIO_D1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G3", "SD_SDIO_D2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G4", "SD_SDIO_D3", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G5", "SD_SDIO_CD_N", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G6", "SD_SDIO_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G7", "AVS_I2S2_SCLK", "n/a", "n/a", "DMIC_CLK_A0", "n/a", "n/a", "n/a", "n/a", + "GPP_G8", "AVS_I2S2_SFRM", "RSVD", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "n/a", + "GPP_G9", "AVS_I2S2_TXD", "RSVD", "RSVD", "DMIC_CLK_A1", "n/a", "n/a", "n/a", "n/a", "GPP_G10", "AVS_I2S2_RXD", "n/a", "n/a", "DMIC_DATA1", "n/a", "n/a", "n/a", "n/a", "GPP_G11", "AVS_I2S3_SCLK", "n/a", "n/a", "DMIC_DATA0", "n/a", "n/a", "n/a", "PSE_TGPIO07", "GPP_G12", "AVS_I2S3_SFRM", "SATA_1_GP", "SATAXPCIE_1", "DMIC_DATA1", "n/a", "n/a", "n/a", "PSE_TGPIO31", @@ -279,16 +279,16 @@ }; const char *const elkhartlake_pch_group_h_names[] = { - "GPP_H00", "PSE_GBE1_INT", "n/a", "n/a", "PSE_UART5_RXD", "n/a", "n/a", "n/a", "n/a", - "GPP_H01", "PSE_GBE1_RST_N", "n/a", "n/a", "PSE_UART5_TXD", "n/a", "n/a", "n/a", "n/a", - "GPP_H02", "PSE_GBE1_AUXTS", "n/a", "n/a", "PSE_UART5_RTS_N", "n/a", "n/a", "n/a", "n/a", - "GPP_H03", "PSE_GBE1_PPS", "n/a", "n/a", "PSE_UART5_CTS_N", "n/a", "n/a", "n/a", "PSE_TGPIO21", - "GPP_H04", "SIO_I2C2_SDA", "n/a", "n/a", "PSE_PWM08", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_H05", "SIO_I2C2_SCL", "n/a", "n/a", "PSE_PWM09", "n/a", "n/a", "n/a", "PSE_TGPIO11", - "GPP_H06", "SIO_I2C3_SDA", "PSE_I2C5_SDA", "n/a", "PSE_PWM10", "n/a", "n/a", "n/a", "n/a", - "GPP_H07", "SIO_I2C3_SCL", "PSE_I2C5_SCL", "n/a", "PSE_PWM11", "n/a", "n/a", "n/a", "n/a", - "GPP_H08", "SIO_I2C4_SDA", "RSVD", "n/a", "PSE_PWM12", "n/a", "n/a", "n/a", "n/a", - "GPP_H09", "SIO_I2C4_SCL", "RSVD", "n/a", "PSE_PWM13", "n/a", "n/a", "n/a", "n/a", + "GPP_H0", "PSE_GBE1_INT", "n/a", "n/a", "PSE_UART5_RXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H1", "PSE_GBE1_RST_N", "n/a", "n/a", "PSE_UART5_TXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H2", "PSE_GBE1_AUXTS", "n/a", "n/a", "PSE_UART5_RTS_N", "n/a", "n/a", "n/a", "n/a", + "GPP_H3", "PSE_GBE1_PPS", "n/a", "n/a", "PSE_UART5_CTS_N", "n/a", "n/a", "n/a", "PSE_TGPIO21", + "GPP_H4", "SIO_I2C2_SDA", "n/a", "n/a", "PSE_PWM08", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_H5", "SIO_I2C2_SCL", "n/a", "n/a", "PSE_PWM09", "n/a", "n/a", "n/a", "PSE_TGPIO11", + "GPP_H6", "SIO_I2C3_SDA", "PSE_I2C5_SDA", "n/a", "PSE_PWM10", "n/a", "n/a", "n/a", "n/a", + "GPP_H7", "SIO_I2C3_SCL", "PSE_I2C5_SCL", "n/a", "PSE_PWM11", "n/a", "n/a", "n/a", "n/a", + "GPP_H8", "SIO_I2C4_SDA", "RSVD", "n/a", "PSE_PWM12", "n/a", "n/a", "n/a", "n/a", + "GPP_H9", "SIO_I2C4_SCL", "RSVD", "n/a", "PSE_PWM13", "n/a", "n/a", "n/a", "n/a", "GPP_H10", "PCIE_CLKREQ4_N", "n/a", "n/a", "PSE_PWM14", "n/a", "n/a", "n/a", "n/a", "GPP_H11", "PCIE_CLKREQ5_N", "n/a", "n/a", "PSE_PWM15", "n/a", "n/a", "n/a", "n/a", "GPP_H12", "PSE_UART1_RXD", "n/a", "n/a", "M2_SKT2_CFG0", "n/a", "n/a", "n/a", "PSE_TGPIO51", @@ -313,14 +313,14 @@ }; const char *const elkhartlake_pch_group_r_names[] = { - "GPP_R00", "HDA_BCLK", "AVS_I2S0_SCLK", "PSE_I2S0_SCLK", "RSVD", "n/a", - "GPP_R01", "HDA_SYNC", "AVS_I2S0_SFRM", "PSE_I2S0_SFRM", "n/a", "n/a", - "GPP_R02", "HDA_SDO", "AVS_I2S0_TXD", "PSE_I2S0_TXD", "RSVD", "DMIC_CLK_B0", - "GPP_R03", "HDA_SDI0", "AVS_I2S0_RXD", "PSE_I2S0_RXD", "RSVD", "DMIC_CLK_B1", - "GPP_R04", "HDA_RST_N", "n/a", "n/a", "n/a", "DMIC_CLK_A1", - "GPP_R05", "HDA_SDI1", "AVS_I2S1_RXD", "n/a", "n/a", "DMIC_DATA1", - "GPP_R06", "n/a", "AVS_I2S1_TXD", "n/a", "n/a", "DMIC_CLK_A0", - "GPP_R07", "n/a", "AVS_I2S1_SFRM", "n/a", "n/a", "DMIC_DATA0", + "GPP_R0", "HDA_BCLK", "AVS_I2S0_SCLK", "PSE_I2S0_SCLK", "RSVD", "n/a", + "GPP_R1", "HDA_SYNC", "AVS_I2S0_SFRM", "PSE_I2S0_SFRM", "n/a", "n/a", + "GPP_R2", "HDA_SDO", "AVS_I2S0_TXD", "PSE_I2S0_TXD", "RSVD", "DMIC_CLK_B0", + "GPP_R3", "HDA_SDI0", "AVS_I2S0_RXD", "PSE_I2S0_RXD", "RSVD", "DMIC_CLK_B1", + "GPP_R4", "HDA_RST_N", "n/a", "n/a", "n/a", "DMIC_CLK_A1", + "GPP_R5", "HDA_SDI1", "AVS_I2S1_RXD", "n/a", "n/a", "DMIC_DATA1", + "GPP_R6", "n/a", "AVS_I2S1_TXD", "n/a", "n/a", "DMIC_CLK_A0", + "GPP_R7", "n/a", "AVS_I2S1_SFRM", "n/a", "n/a", "DMIC_DATA0", }; const struct gpio_group elkhartlake_pch_group_r = { @@ -348,8 +348,8 @@ "GPIO_RSVD_27", "n/a", "GPIO_RSVD_28", "n/a", "GPIO_RSVD_29", "n/a", - "GPP_S00", "n/a", - "GPP_S01", "n/a", + "GPP_S0", "n/a", + "GPP_S1", "n/a", }; const struct gpio_group elkhartlake_pch_group_s = { @@ -360,16 +360,16 @@ }; const char *const elkhartlake_pch_group_t_names[] = { - "GPP_T00", "PSE_QEPA2", "n/a", "SIO_I2C6_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", - "GPP_T01", "PSE_QEPB2", "n/a", "SIO_I2C6_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", - "GPP_T02", "PSE_QEPI2", "n/a", "SIO_I2C7_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", - "GPP_T03", "n/a", "n/a", "SIO_I2C7_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", - "GPP_T04", "PSE_GBE0_INT", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T05", "PSE_GBE0_RST_N", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T06", "PSE_GBE0_AUXTS", "USB2_OC1_N", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", - "GPP_T07", "PSE_GBE0_PPS", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO59", - "GPP_T08", "USB2_OC2_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO22", - "GPP_T09", "PSE_HSUART2_EN", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_T0", "PSE_QEPA2", "n/a", "SIO_I2C6_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO08", + "GPP_T1", "PSE_QEPB2", "n/a", "SIO_I2C6_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO09", + "GPP_T2", "PSE_QEPI2", "n/a", "SIO_I2C7_SDA", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO07", + "GPP_T3", "n/a", "n/a", "SIO_I2C7_SCL", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", + "GPP_T4", "PSE_GBE0_INT", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T5", "PSE_GBE0_RST_N", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T6", "PSE_GBE0_AUXTS", "USB2_OC1_N", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", + "GPP_T7", "PSE_GBE0_PPS", "n/a", "n/a", "RSVD", "n/a", "n/a", "n/a", "PSE_TGPIO59", + "GPP_T8", "USB2_OC2_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO22", + "GPP_T9", "PSE_HSUART2_EN", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_T10", "PSE_HSUART2_RE", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "GPP_T11", "USB2_OC3_N", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO06", "GPP_T12", "PSE_UART2_RXD", "SIO_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -386,16 +386,16 @@ }; const char *const elkhartlake_pch_group_u_names[] = { - "GPP_U00", "GBE_INT", "PSE_I2C6_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U01", "GBE_RST_N", "PSE_I2C6_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U02", "GBE_PPS", "PSE_I2C7_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U03", "GBE_AUXTS", "PSE_I2C7_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", - "GPP_U04", "ISI_SPIM_CS", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "n/a", - "GPP_U05", "ISI_SPIM_SCLK", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "n/a", - "GPP_U06", "ISI_SPIM_MISO", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "n/a", - "GPP_U07", "PSE_QEPA3", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_U08", "ISI_SPIS_CS", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO10", - "GPP_U09", "ISI_SPIS_SCLK", "ISI_I2CS_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", + "GPP_U0", "GBE_INT", "PSE_I2C6_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U1", "GBE_RST_N", "PSE_I2C6_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U2", "GBE_PPS", "PSE_I2C7_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U3", "GBE_AUXTS", "PSE_I2C7_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_U4", "ISI_SPIM_CS", "n/a", "RSVD", "PSE_SPI1_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPP_U5", "ISI_SPIM_SCLK", "n/a", "RSVD", "PSE_SPI1_CLK", "n/a", "n/a", "n/a", "n/a", + "GPP_U6", "ISI_SPIM_MISO", "n/a", "RSVD", "PSE_SPI1_MISO", "n/a", "n/a", "n/a", "n/a", + "GPP_U7", "PSE_QEPA3", "n/a", "RSVD", "PSE_SPI1_MOSI", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_U8", "ISI_SPIS_CS", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO10", + "GPP_U9", "ISI_SPIS_SCLK", "ISI_I2CS_SCL", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", "GPP_U10", "ISI_SPIS_MISO", "ISI_I2CS_SDA", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO12", "GPP_U11", "PSE_QEPB3", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "PSE_TGPIO11", "GPP_U12", "ISI_CHX_OKNOK_0", "n/a", "RSVD", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -420,16 +420,16 @@ }; const char *const elkhartlake_pch_group_v_names[] = { - "GPP_V00", "EMMC_CMD", - "GPP_V01", "EMMC_DATA0", - "GPP_V02", "EMMC_DATA1", - "GPP_V03", "EMMC_DATA2", - "GPP_V04", "EMMC_DATA3", - "GPP_V05", "EMMC_DATA4", - "GPP_V06", "EMMC_DATA5", - "GPP_V07", "EMMC_DATA6", - "GPP_V08", "EMMC_DATA7", - "GPP_V09", "EMMC_RCLK", + "GPP_V0", "EMMC_CMD", + "GPP_V1", "EMMC_DATA0", + "GPP_V2", "EMMC_DATA1", + "GPP_V3", "EMMC_DATA2", + "GPP_V4", "EMMC_DATA3", + "GPP_V5", "EMMC_DATA4", + "GPP_V6", "EMMC_DATA5", + "GPP_V7", "EMMC_DATA6", + "GPP_V8", "EMMC_DATA7", + "GPP_V9", "EMMC_RCLK", "GPP_V10", "EMMC_CLK", "GPP_V11", "EMMC_RST_N", "GPP_V12", "PSE_TGPIO00", -- To view, visit https://review.coreboot.org/c/coreboot/+/84190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Gerrit-Change-Number: 84190 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Fix timer reset in BL31
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83928?usp=email ) Change subject: soc/mediatek/mt8196: Fix timer reset in BL31 ...................................................................... soc/mediatek/mt8196: Fix timer reset in BL31 After reboot, the system does not need to serve pending IRQ from systimer. Therefore, clear systimer IRQ pending bits in init_timer(). For that to work, the systimer compensation version 2.0 needs to be enabled. TEST=Build pass and timestamp is not reset in ATF and payload BUG=b:343881008 Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Signed-off-by: Zhanzhan Ge <zhanzhan.ge(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/timer.h M src/soc/mediatek/mt8196/timer.c A src/soc/mediatek/mt8196/timer_prepare.c 4 files changed, 72 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b11778f..388dad1 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -6,7 +6,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c gpio.c gpio_eint.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += spi.c -all-y += timer.c +all-y += timer.c timer_prepare.c all-y += ../common/uart.c bootblock-y += bootblock.c diff --git a/src/soc/mediatek/mt8196/include/soc/timer.h b/src/soc/mediatek/mt8196/include/soc/timer.h index d6422c5..f6841fc 100644 --- a/src/soc/mediatek/mt8196/include/soc/timer.h +++ b/src/soc/mediatek/mt8196/include/soc/timer.h @@ -2,12 +2,44 @@ /* * This file is created based on MT8196 Functional Specification - * Chapter number: 5.13 + * Chapter number: 1.2 2.2 */ #ifndef SOC_MEDIATEK_MT8196_TIMER_H #define SOC_MEDIATEK_MT8196_TIMER_H #include <soc/timer_v2.h> +#include <stdint.h> + +DEFINE_BITFIELD(COMP_FEATURE, 12, 10) +DEFINE_BITFIELD(COMP_FEATURE_TIE, 4, 3) +DEFINE_BITFIELD(REV_SET, 18, 17) +DEFINE_BITFIELD(SYST_CON, 4, 0) + +#define SYST_CON_EN BIT(0) +#define SYST_CON_IRQ_CLR BIT(4) +#define REV_CLR_EN 0x3 +#define COMP_FEATURE_20_EN 0x2 +#define COMP_FEATURE_TIE_EN 0x1 +#define COMP_FEATURE_CLR 0 +#define COMP_FEATURE_TIE_CLR 0 +#define SYSTIMER_CNT 8 +#define SYST_CON_CLR 0 + +struct systimer { + u32 cntcr; + u32 reserved; + u32 cntcv_l; + u32 cntcv_h; + u32 reserved1[0x30]; + struct { + u32 con; + u32 val; + } cnttval[SYSTIMER_CNT]; +}; + +check_member(systimer, cntcr, 0x0); +check_member(systimer, cntcv_l, 0x0008); +check_member(systimer, cntcv_h, 0x000c); #endif diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c index 9d8dd7a..bf3f3ce 100644 --- a/src/soc/mediatek/mt8196/timer.c +++ b/src/soc/mediatek/mt8196/timer.c @@ -3,8 +3,11 @@ #include <arch/lib_helpers.h> #include <commonlib/helpers.h> #include <delay.h> +#include <soc/timer.h> void init_timer(void) { - raw_write_cntfrq_el0(13 * MHz); + timer_prepare(); + + raw_write_cntfrq_el0(GPT_MHZ * MHz); } diff --git a/src/soc/mediatek/mt8196/timer_prepare.c b/src/soc/mediatek/mt8196/timer_prepare.c new file mode 100644 index 0000000..08496e8 --- /dev/null +++ b/src/soc/mediatek/mt8196/timer_prepare.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 1.2 2.2 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/timer.h> + +static void clear_systimer(struct systimer *const mtk_systimer) +{ + unsigned int id = 0; + + for (id = 0; id < SYSTIMER_CNT; id++) { + u32 *cnttval_con = &mtk_systimer->cnttval[id].con; + WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_EN); + SET32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_IRQ_CLR); + WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_CLR); + } + + SET32_BITFIELDS(&mtk_systimer->cntcr, REV_SET, REV_CLR_EN); +} + +void timer_prepare(void) +{ + struct systimer *mtk_systimer = (void *)SYSTIMER_BASE; + + SET32_BITFIELDS(&mtk_systimer->cntcr, + COMP_FEATURE, COMP_FEATURE_CLR | COMP_FEATURE_20_EN, + COMP_FEATURE_TIE, COMP_FEATURE_TIE_CLR | COMP_FEATURE_TIE_EN); + clear_systimer(mtk_systimer); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Gerrit-Change-Number: 83928 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhanzhan Ge <zhanzhan.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by default
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84544?usp=email ) Change subject: drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by default ...................................................................... drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by default This should be the sane default, as having this option enabled when the AT24RF08C (Asset Identification EEPROM) is not present on the mainboard can cause SMBIOS table entries to become "*INVALID*". This can, for example, result in strange hostnames when an OS installer uses SMBIOS information to automatically generate one. On the other hand, the coreboot generated SMBIOS tables will at least always contain basic information. Therefore, this driver should be treated as an enhancement rather than a default. Currently, the following mainboards have this option disabled: - ThinkCentre M710s - ThinkCentre M700 / M900 Tiny - Haswell ThinkPads - ThinkPad T440p - ThinkPad W541 Therefore, we can remove this option entirely on these mainboards. Note that there may be other mainboards which do not have this chip present but still have the option enabled. However, this requires a more detailed investigation which would be out of scope of this change. TESTS=Timeless builds on lenovo mainboards produce the same binary. config INCLUDE_CONFIG_FILE default n Was temporarily added to `mb/lenovo/Kconfig` during these tests, as while the configuration does not change, the order of entries do. Therefore, technically producing a different binary when included. Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/i2c/at24rf08c/Kconfig M src/mainboard/lenovo/haswell/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/m900_tiny/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig M src/mainboard/lenovo/thinkcentre_m710s/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x60/Kconfig 23 files changed, 20 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/drivers/i2c/at24rf08c/Kconfig b/src/drivers/i2c/at24rf08c/Kconfig index 5834cff..a930a46 100644 --- a/src/drivers/i2c/at24rf08c/Kconfig +++ b/src/drivers/i2c/at24rf08c/Kconfig @@ -2,5 +2,4 @@ config DRIVER_LENOVO_SERIALS bool - default y if VENDOR_LENOVO select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig index a5c8054..b2fc97d 100644 --- a/src/mainboard/lenovo/haswell/Kconfig +++ b/src/mainboard/lenovo/haswell/Kconfig @@ -72,10 +72,6 @@ int default 2 -config DRIVER_LENOVO_SERIALS - bool - default n - config PS2K_EISAID default "LEN0071" diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 597fa48..9912098 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select EC_LENOVO_PMH7 select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index ffcf058..8ad36e0 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -2,6 +2,7 @@ if BOARD_LENOVO_THINKCENTRE_M900_TINY +# TODO: fix and enable DRIVER_LENOVO_SERIALS config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 @@ -37,8 +38,4 @@ config DIMM_SPD_SIZE default 512 #DDR4 -# TODO: fix and enable -config DRIVER_LENOVO_SERIALS - default n - endif diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 94b8c84..49c8820 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 + select DRIVER_LENOVO_SERIALS select EC_ACPI select EC_COMPAL_ENE932 select GFX_GMA_PANEL_1_ON_LVDS diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 1951d55..5afcde8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -23,6 +23,7 @@ select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 select DRIVERS_LENOVO_HYBRID_GRAPHICS + select DRIVER_LENOVO_SERIALS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 2ee8530..9c78cb1 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -25,6 +25,7 @@ select H8_HAS_BAT_THRESHOLDS_IMPL select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_RICOH_RCE822 + select DRIVER_LENOVO_SERIALS config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 5e9dc69..e2137a3 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -19,6 +19,7 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select DRIVERS_RICOH_RCE822 + select DRIVER_LENOVO_SERIALS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index f71722d..5ed1fde 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select DRIVERS_LENOVO_HYBRID_GRAPHICS + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select EC_LENOVO_PMH7 select GFX_GMA_PANEL_1_ON_LVDS diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 3d2812c..e136871 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_12288 select DRIVERS_LENOVO_HYBRID_GRAPHICS + select DRIVER_LENOVO_SERIALS select DRIVERS_RICOH_RCE822 select EC_LENOVO_H8 select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 45a06f5..9a7a91b 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -26,6 +26,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S + select DRIVER_LENOVO_SERIALS select HAVE_SPD_IN_CBFS if BOARD_LENOVO_T431S # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 54447c7..663113b 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -23,6 +23,7 @@ select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT if BOARD_LENOVO_T520 select MAINBOARD_USES_IFD_GBE_REGION + select DRIVER_LENOVO_SERIALS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f237f90..a797656 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -4,6 +4,7 @@ def_bool n select BOARD_ROMSIZE_KB_12288 select DRIVERS_LENOVO_HYBRID_GRAPHICS + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select EC_LENOVO_PMH7 select GFX_GMA_PANEL_1_ON_LVDS diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a7abbcd..ec3a6e0 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -15,6 +15,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select DRIVERS_I2C_CK505 + select DRIVER_LENOVO_SERIALS select HAVE_OPTION_TABLE select INTEL_INT15 select HAVE_MP_TABLE diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index 353d323..e24d502 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -14,6 +14,7 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select DRIVERS_I2C_CK505 + select DRIVER_LENOVO_SERIALS select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig index c9bcd75..c01aaec 100644 --- a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig @@ -23,7 +23,4 @@ config MAINBOARD_PART_NUMBER default "ThinkCentre M710s" -config DRIVER_LENOVO_SERIALS - default n - endif # BOARD_LENOVO_THINKCENTRE_M710S diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index ab421f2..67d7980 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select GFX_GMA_PANEL_1_ON_LVDS select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 0604202..4e4c58b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_12288 select DRIVERS_RICOH_RCE822 + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select EC_LENOVO_PMH7 select GFX_GMA_PANEL_1_ON_LVDS diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 5f1298b..29e2f6c 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -22,6 +22,7 @@ select INTEL_INT15 select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM + select DRIVER_LENOVO_SERIALS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index dcf13ec..8517232 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -19,6 +19,7 @@ select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM + select DRIVER_LENOVO_SERIALS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 453601c..e6a2e66 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select DRIVERS_RICOH_RCE822 + select DRIVER_LENOVO_SERIALS select EC_LENOVO_H8 select EC_LENOVO_PMH7 select GFX_GMA_PANEL_1_ON_LVDS diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index d14730a..1d04af9 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -21,6 +21,7 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select DRIVERS_RICOH_RCE822 + select DRIVER_LENOVO_SERIALS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index eaf3700..0f12a92 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -15,6 +15,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select DRIVERS_I2C_CK505 + select DRIVER_LENOVO_SERIALS select HAVE_OPTION_TABLE select INTEL_INT15 select HAVE_CMOS_DEFAULT -- To view, visit https://review.coreboot.org/c/coreboot/+/84544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51 Gerrit-Change-Number: 84544 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDs
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84529?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDs ...................................................................... mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDs Add two new memory parts 1. K3KL8L80CM-MGCT (Samsung) 2. H58G56BK8BX068 (Hynix) BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/riven/memory/Makefile.mk M src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk index 0288c51..ecca8b5 100644 --- a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk @@ -8,3 +8,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = H58G56BK8BX068 diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt index f767092..7f8976c 100644 --- a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt @@ -10,3 +10,5 @@ K3LKLKL0EM-MGCN 2 (0010) K3LKBKB0BM-MGCP 3 (0011) H9JCNNNCP3MLYR-N6E 0 (0000) +K3KL8L80CM-MGCT 4 (0100) +H58G56BK8BX068 5 (0101) diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt index b08faac..2c18a19 100644 --- a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt @@ -15,3 +15,5 @@ K3LKLKL0EM-MGCN K3LKBKB0BM-MGCP H9JCNNNCP3MLYR-N6E +K3KL8L80CM-MGCT +H58G56BK8BX068 -- To view, visit https://review.coreboot.org/c/coreboot/+/84529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e Gerrit-Change-Number: 84529 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/starlabs/byte_adl/mk_ii: Correct number of jacks in hda_verb.c
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84502?usp=email ) Change subject: mb/starlabs/byte_adl/mk_ii: Correct number of jacks in hda_verb.c ...................................................................... mb/starlabs/byte_adl/mk_ii: Correct number of jacks in hda_verb.c This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c index 46c8738..9b87198 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c @@ -7,7 +7,7 @@ /* coreboot specific header */ 0x14f11f87, /* Codec Vendor / Device ID: SoundWire SN6140 */ 0x14f1035e, /* Subsystem ID */ - 17, /* Number of jacks (NID entries) */ + 19, /* Number of jacks (NID entries) */ /* Reset Codec First */ AZALIA_RESET(0x1), -- To view, visit https://review.coreboot.org/c/coreboot/+/84502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b Gerrit-Change-Number: 84502 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google: Correct number of jacks in hda_verb.c
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84414?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google: Correct number of jacks in hda_verb.c ...................................................................... mb/google: Correct number of jacks in hda_verb.c This corrects the mismatch found in the verb tables of Monroe Chromebase and Link Chromebook. The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This was found due to the `_Static_assert()` from CB:84360 failing. TEST=Tested on LINK under Linux and Win11, audio working properly under both. Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/link/hda_verb.c 2 files changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 064bebf..3b529e2 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -6,7 +6,7 @@ /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 0x10ec0283, // Subsystem ID - 0x0000000e, // Number of jacks (NID entries) + 0x00000010, // Number of jacks (NID entries) 0x0017ff00, // Function Reset 0x0017ff00, // Double Function Reset diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c index 9381b57..d3309cd 100644 --- a/src/mainboard/google/link/hda_verb.c +++ b/src/mainboard/google/link/hda_verb.c @@ -6,7 +6,7 @@ /* coreboot specific header */ 0x11020011, // Codec Vendor / Device ID: Creative CA0132 0x10280550, // Subsystem ID - 0x00000014, // Number of jacks + Number of Malcolm setup blocks. + 0x00000015, // Number of jacks + Number of Malcolm setup blocks. /* Malcolm Setup */ @@ -62,6 +62,9 @@ /* Enable and set EAPD pin for headphone jack */ AZALIA_VERB_12B(0x0, 0x10, 0x78d, 0x2), + AZALIA_VERB_12B(0x0, 0x10, 0x78d, 0x2), /* Padding */ + AZALIA_VERB_12B(0x0, 0x10, 0x78d, 0x2), /* Padding */ + AZALIA_VERB_12B(0x0, 0x10, 0x78d, 0x2), /* Padding */ /* Pin Widget Verb Table */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827 Gerrit-Change-Number: 84414 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: mb/samsung/lumpy: Correct number of jacks in hda_verb.c
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84395?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/samsung/lumpy: Correct number of jacks in hda_verb.c ...................................................................... mb/samsung/lumpy: Correct number of jacks in hda_verb.c The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This has not been tested. This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/samsung/lumpy/hda_verb.c 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index d18d8d2..b3350a1 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -6,12 +6,15 @@ /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 0x152D0924, // Subsystem ID - 0x00000007, // Number of jacks + 0x00000008, // Number of jacks /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x152D0924 */ AZALIA_SUBVENDOR(0, 0x152D0924), 0x00170500, + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ /* Pin Widget Verb Table */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Gerrit-Change-Number: 84395 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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