coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: mb/samsung/lumpy: Correct number of jacks in hda_verb.c
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84395?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/samsung/lumpy: Correct number of jacks in hda_verb.c ...................................................................... mb/samsung/lumpy: Correct number of jacks in hda_verb.c The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This has not been tested. This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/samsung/lumpy/hda_verb.c 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index d18d8d2..b3350a1 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -6,12 +6,15 @@ /* coreboot specific header */ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 0x152D0924, // Subsystem ID - 0x00000007, // Number of jacks + 0x00000008, // Number of jacks /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x152D0924 */ AZALIA_SUBVENDOR(0, 0x152D0924), 0x00170500, + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ /* Pin Widget Verb Table */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Gerrit-Change-Number: 84395 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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Change in coreboot[master]: libgfxinit: Allow to configure screen rotation
by Nico Huber (Code Review) 30 Sep '24

30 Sep '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38922 ) Change subject: libgfxinit: Allow to configure screen rotation ...................................................................... libgfxinit: Allow to configure screen rotation This allows us to configure a default screen rotation in 90 degree steps. The framebuffer contents will then be displayed by the same amount in the other direction. The 90 and 270 degree settings are only supported by newer display engines, from Skylake / Apollo Lake on. Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/Kconfig M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb 2 files changed, 47 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38922/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..6859c24 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -478,6 +478,27 @@ Set the maximum height of the framebuffer. This may help with default fonts too tiny for high-resolution displays. +choice DEFAULT_SCREEN_ROTATION + prompt "Default screen rotation" + depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT + default DEFAULT_SCREEN_ROTATION_NONE + +config DEFAULT_SCREEN_ROTATION_NONE + bool "None" + +config DEFAULT_SCREEN_ROTATION_90 + bool "90 degrees CCW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +config DEFAULT_SCREEN_ROTATION_180 + bool "180 degrees" + +config DEFAULT_SCREEN_ROTATION_270 + bool "90 degrees CW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +endchoice + endmenu # "Display" config PCI diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 1393784..014e92b 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -54,9 +54,20 @@ ---------------------------------------------------------------------------- + procedure Screen_Rotation (rotation : out Rotation_Type) + is + begin + rotation := + (if Config.DEFAULT_SCREEN_ROTATION_90 then Rotated_90 + elsif Config.DEFAULT_SCREEN_ROTATION_180 then Rotated_180 + elsif Config.DEFAULT_SCREEN_ROTATION_270 then Rotated_270 + else No_Rotation); + end Screen_Rotation; + procedure gfxinit (lightup_ok : out Interfaces.C.int) is use type pos32; + use type word32; use type word64; ports : Port_List; @@ -84,10 +95,21 @@ end loop; fb := configs (Primary).Framebuffer; - fb.Width := Width_Type (min_h); - fb.Height := Height_Type (min_v); - fb.Stride := Div_Round_Up (fb.Width, 16) * 16; - fb.V_Stride := fb.Height; + Screen_Rotation (fb.Rotation); + + if fb.Rotation = Rotated_90 or fb.Rotation = Rotated_270 then + fb.Width := Width_Type (min_v); + fb.Height := Height_Type (min_h); + fb.Stride := Div_Round_Up (fb.Width, 32) * 32; + fb.V_Stride := Div_Round_Up (fb.Height, 32) * 32; + fb.Tiling := Y_Tiled; + fb.Offset := word32 (GTT_Rotation_Offset) * GTT_Page_Size; + else + fb.Width := Width_Type (min_h); + fb.Height := Height_Type (min_v); + fb.Stride := Div_Round_Up (fb.Width, 16) * 16; + fb.V_Stride := fb.Height; + end if; for i in Pipe_Index loop exit when configs (i).Port = Disabled; -- To view, visit https://review.coreboot.org/c/coreboot/+/38922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Gerrit-Change-Number: 38922 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER he...
by Felix Held (Code Review) 30 Sep '24

30 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84492?usp=email ) Change subject: soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help text ...................................................................... soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help text regist*re*s → regist*er*s Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/soc/intel/common/block/systemagent/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nicholas Sudsgaard: Looks good to me, approved diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 42d579a..b075c92 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -53,6 +53,6 @@ bool default y help - Specify if the SOC has BDSM and BGSM registres. + Specify if the SOC has BDSM and BGSM registers. endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Gerrit-Change-Number: 84492 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Felix Singer (Code Review) 30 Sep '24

30 Sep '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email ) Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... util/superiotool/ite: Add extra dumps for IT8613E EC IT8613E EC space is divided into 3 banks selectable by EC index 0x06 bits 6:5. Bank0 mostly contains the ITE EC registers known by coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature reading registers. Bank2, however, contains additional registers used to select the temperature source reported in TMPIN reading registers, PECI bridge registers as well as FAN2-5 controls and extra vectors. Dump the additional banks using extra-selectors. Based on non-public IT8613E Preliminary Specification V0.3. TEST=Perform the IT8613E dump on Hardkernel ODROID H4+. Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maxim <max.senia.poliak(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marvin Drees <marvin.drees(a)9elements.com> --- M util/superiotool/ite.c 1 file changed, 42 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved Alicja Michalska: Looks good to me, but someone else must approve Maxim: Looks good to me, but someone else must approve Marvin Drees: Looks good to me, but someone else must approve build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 91decc6..22b5620 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -7,6 +7,15 @@ #define CHIP_VERSION_REG 0x22 #define ISA_PNP_ADDR 0x279 +/* IT8613 EC SMI# Mask Register 3 (06h): BANK_SEL[6-5] */ +#define IT8613_EC_BANK_SEL(bank) \ + { \ + .idx = 0x06, \ + .mask = 0x60, \ + .val = (((bank) & 3) << 5) \ + } + + static const struct superio_registers reg_table[] = { {0x5570, "IT5570E", { {NOLDN, NULL, @@ -1380,7 +1389,7 @@ static const struct superio_registers ec_table[] = { {0x8613, "IT8613E", { - {NOLDN, NULL, + {NOLDN, "BANK0", {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0e,0x0f,0x11,0x12,0x13,0x14,0x16, 0x17,0x19,0x1a,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22, @@ -1408,7 +1417,38 @@ NANA,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,MISC,0x00,0x00,0x00,0x00,0x00,NANA,0x00,NANA, 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA, - NANA,NANA,NANA,EOT}}, + NANA,NANA,NANA,EOT}, + IT8613_EC_BANK_SEL(0)}, + {NOLDN, "BANK1", + {0xc0,0xc1,0xc2,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6, + 0xd7,0xd8,0xd9,0xda,0xdb,0xdc,0xe0,0xe1,0xe2,0xe3, + 0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed, + 0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}, + IT8613_EC_BANK_SEL(1)}, + {NOLDN, "BANK2", + {0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26, + 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x50,0x51,0x52,0x53,0x54,0x55, + 0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f, + 0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76, + EOT}, + {0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x00,0x00, + 0x00,0x00,0x00,NANA,NANA,0x00,NANA,NANA,NANA,NANA, + EOT}, + IT8613_EC_BANK_SEL(2)}, {EOT}}}, {0x8625, "IT8625E", { {NOLDN, NULL, -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Felix Singer (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Angel Pons, Felix Held, Michał Żygowski. Felix Singer has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email ) Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:53:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/cnvi: Add CNMT Mutex
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84598?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/cnvi: Add CNMT Mutex ...................................................................... soc/intel/common/cnvi: Add CNMT Mutex Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84598/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Gerrit-Change-Number: 84598 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email ) Change subject: soc/amd/glinda: Update pci int defs ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84375/comment/d25f779b_7ae78fa9?us… : PS5, Line 8: > A summary of the changes would be nice. It is basically just checking which IRQs are still present in the datasheet and updating them accordingly. The code diff is basically the best summary for this particular change. https://review.coreboot.org/c/coreboot/+/84375/comment/9b165ff6_1f3444ed?us… : PS5, Line 11: > Were you able to boot test this? I tested it on the birman+. But with a lot patches in between that I am going to upstream soon for the birman+ board. I just wanted to avoid creating 1 big patch train. -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:25:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Maximilian Brune. Hello Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84375?usp=email to look at the new patch set (#6). Change subject: soc/amd/glinda: Update pci int defs ...................................................................... soc/amd/glinda: Update pci int defs Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h 3 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84375/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/common/cnvi: Add CNMT Mutex
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84598?usp=email ) Change subject: soc/intel/common/cnvi: Add CNMT Mutex ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Gerrit-Change-Number: 84598 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:12:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Sean Rhodes has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/84596?usp=email ) Change subject: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree ...................................................................... soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree Hook up CNVi Bluetooth UPDs to the devicetree, and set them to true so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/chipset.cb M src/soc/intel/cannonlake/chipset_pch_h.cb M src/soc/intel/cannonlake/fsp_params.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84596/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Gerrit-Change-Number: 84596 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2024