coreboot-gerrit September 2024

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Felix Singer (Code Review) 30 Sep '24

30 Sep '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email ) Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... util/superiotool/ite: Add extra dumps for IT8613E EC IT8613E EC space is divided into 3 banks selectable by EC index 0x06 bits 6:5. Bank0 mostly contains the ITE EC registers known by coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature reading registers. Bank2, however, contains additional registers used to select the temperature source reported in TMPIN reading registers, PECI bridge registers as well as FAN2-5 controls and extra vectors. Dump the additional banks using extra-selectors. Based on non-public IT8613E Preliminary Specification V0.3. TEST=Perform the IT8613E dump on Hardkernel ODROID H4+. Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maxim <max.senia.poliak(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marvin Drees <marvin.drees(a)9elements.com> --- M util/superiotool/ite.c 1 file changed, 42 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved Alicja Michalska: Looks good to me, but someone else must approve Maxim: Looks good to me, but someone else must approve Marvin Drees: Looks good to me, but someone else must approve build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 91decc6..22b5620 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -7,6 +7,15 @@ #define CHIP_VERSION_REG 0x22 #define ISA_PNP_ADDR 0x279 +/* IT8613 EC SMI# Mask Register 3 (06h): BANK_SEL[6-5] */ +#define IT8613_EC_BANK_SEL(bank) \ + { \ + .idx = 0x06, \ + .mask = 0x60, \ + .val = (((bank) & 3) << 5) \ + } + + static const struct superio_registers reg_table[] = { {0x5570, "IT5570E", { {NOLDN, NULL, @@ -1380,7 +1389,7 @@ static const struct superio_registers ec_table[] = { {0x8613, "IT8613E", { - {NOLDN, NULL, + {NOLDN, "BANK0", {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0e,0x0f,0x11,0x12,0x13,0x14,0x16, 0x17,0x19,0x1a,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22, @@ -1408,7 +1417,38 @@ NANA,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,MISC,0x00,0x00,0x00,0x00,0x00,NANA,0x00,NANA, 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA, - NANA,NANA,NANA,EOT}}, + NANA,NANA,NANA,EOT}, + IT8613_EC_BANK_SEL(0)}, + {NOLDN, "BANK1", + {0xc0,0xc1,0xc2,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6, + 0xd7,0xd8,0xd9,0xda,0xdb,0xdc,0xe0,0xe1,0xe2,0xe3, + 0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed, + 0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}, + IT8613_EC_BANK_SEL(1)}, + {NOLDN, "BANK2", + {0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26, + 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x50,0x51,0x52,0x53,0x54,0x55, + 0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f, + 0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76, + EOT}, + {0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x00,0x00, + 0x00,0x00,0x00,NANA,NANA,0x00,NANA,NANA,NANA,NANA, + EOT}, + IT8613_EC_BANK_SEL(2)}, {EOT}}}, {0x8625, "IT8625E", { {NOLDN, NULL, -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/superiotool/ite: Add extra dumps for IT8613E EC
by Felix Singer (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Angel Pons, Felix Held, Michał Żygowski. Felix Singer has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email ) Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6 Gerrit-Change-Number: 80318 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:53:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/cnvi: Add CNMT Mutex
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84598?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/cnvi: Add CNMT Mutex ...................................................................... soc/intel/common/cnvi: Add CNMT Mutex Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84598/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Gerrit-Change-Number: 84598 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email ) Change subject: soc/amd/glinda: Update pci int defs ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84375/comment/d25f779b_7ae78fa9?us… : PS5, Line 8: > A summary of the changes would be nice. It is basically just checking which IRQs are still present in the datasheet and updating them accordingly. The code diff is basically the best summary for this particular change. https://review.coreboot.org/c/coreboot/+/84375/comment/9b165ff6_1f3444ed?us… : PS5, Line 11: > Were you able to boot test this? I tested it on the birman+. But with a lot patches in between that I am going to upstream soon for the birman+ board. I just wanted to avoid creating 1 big patch train. -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:25:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Maximilian Brune. Hello Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84375?usp=email to look at the new patch set (#6). Change subject: soc/amd/glinda: Update pci int defs ...................................................................... soc/amd/glinda: Update pci int defs Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h 3 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84375/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/common/cnvi: Add CNMT Mutex
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84598?usp=email ) Change subject: soc/intel/common/cnvi: Add CNMT Mutex ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Gerrit-Change-Number: 84598 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:12:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Sean Rhodes has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/84596?usp=email ) Change subject: soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree ...................................................................... soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree Hook up CNVi Bluetooth UPDs to the devicetree, and set them to true so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/chipset.cb M src/soc/intel/cannonlake/chipset_pch_h.cb M src/soc/intel/cannonlake/fsp_params.c 4 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84596/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Gerrit-Change-Number: 84596 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update fsp submodule to upstream main
by Felix Singer (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Sean Rhodes. Felix Singer has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84597?usp=email ) Change subject: Update fsp submodule to upstream main ...................................................................... Patch Set 1: (1 comment) File 3rdparty/fsp: https://review.coreboot.org/c/coreboot/+/84597/comment/1b491bf0_1dfb5e06?us… : PS1, Line 1: Subproject commit bb12f17b07700a40c0033da345eae0c1cd487b73 The latest commit has a different ID 02b30da989444aa988ebb00c00c414bb662babd3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib414495bd2b7e6fe363277bad1031e06ab8d503c Gerrit-Change-Number: 84597 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 10:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Update fsp submodule to upstream main
by Sean Rhodes (Code Review) 30 Sep '24

30 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84597?usp=email ) Change subject: Update fsp submodule to upstream main ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib414495bd2b7e6fe363277bad1031e06ab8d503c Gerrit-Change-Number: 84597 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 30 Sep 2024 09:55:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: vendorcode/amd/fsp/glinda: port usb_phy_config structure
by Maximilian Brune (Code Review) 30 Sep '24

30 Sep '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, ritul guru. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84435?usp=email ) Change subject: vendorcode/amd/fsp/glinda: port usb_phy_config structure ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84435/comment/40cd8428_f02ff288?us… : PS3, Line 7: Porting glinda specific usb_phy_config structure > nit, please change this to simply "port usb_phy_config structure" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0603f5da689b6738ea54305a665b150121bc520c Gerrit-Change-Number: 84435 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 09:54:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit September 2024