coreboot-gerrit August 2024

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[S] Change in coreboot[main]: tree: Use boolean for lpss_s0ix_enable
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84160?usp=email ) Change subject: tree: Use boolean for lpss_s0ix_enable ...................................................................... tree: Use boolean for lpss_s0ix_enable Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/84160/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index c6bfe54..138499c 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -52,7 +52,7 @@ register "slp_s3_assertion_width_usecs" = "28000" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2b3f64c..1192a5f 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -63,7 +63,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 80060f1..df39932 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -63,7 +63,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a422b77..022dc8b 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -63,7 +63,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index b6cf852..f97614d 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -60,7 +60,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index c46ca6e..fd30ce7 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -63,7 +63,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 294d468..7a46e10 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -64,7 +64,7 @@ register "hdaudio_bios_config_lockdown" = "1" # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" + register "lpss_s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this -- To view, visit https://review.coreboot.org/c/coreboot/+/84160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Gerrit-Change-Number: 84160 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: tree: Use boolean for s0ix_enable
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84159?usp=email ) Change subject: tree: Use boolean for s0ix_enable ...................................................................... tree: Use boolean for s0ix_enable Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/aoostar/wtr_r1/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/cwwk/adl/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/tigerlake/chip.h 43 files changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84159/1 diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index 101bb99..a802cca 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -14,7 +14,7 @@ register "dptf_enable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "common_soc_config" = "{ .i2c[0] = { diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 5e93271..730f5ef 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -1,5 +1,5 @@ chip soc/intel/cannonlake - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "common_soc_config" = "{ /* Touchpad */ .i2c[0] = { diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 15ec3b2..c4c5e8c 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/alderlake - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 2ded452..49db518 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -17,7 +17,7 @@ chip cpu/intel/haswell device cpu_cluster 0 on ops broadwell_cpu_bus_ops end - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index be96e95..d1e217b 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -14,7 +14,7 @@ chip cpu/intel/haswell device cpu_cluster 0 on end - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 3de469ec..b0b8a60 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -16,7 +16,7 @@ device cpu_cluster 0 on end # Disable S0ix for now - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "vr_config" = "{ .slow_ramp_rate_set = 3, diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 22e15ac..b900af1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -15,7 +15,7 @@ register "sagv" = "SaGv_Enabled" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 38535a4..2ba54bc 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -15,7 +15,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0290181..e07cf2a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -12,7 +12,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 4372888..f91b088 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -12,7 +12,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index aac4bca..3d28ed3 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -29,7 +29,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ffc3a56..ad5b943 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -24,7 +24,7 @@ register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index a5b346c..868342b 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -24,7 +24,7 @@ register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 534db38..cc2b66d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -145,7 +145,7 @@ register "SdCardPowerEnableActiveHigh" = "1" # Enable S0ix support - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Display related UPDs # Select eDP for port A diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 302a09e..7238a06 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -39,7 +39,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 49ff8dd..2fe3e46 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ }" # Enable S0i3 support - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable STT support register "stt_control" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 39cea80..8c33f02 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 9e8e96a..08880cb 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index c0ef101..2cfa075 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index f0f9598..18c4192 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 7626083..58c725e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index d3038f5..9e8f870 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fcaa730..7eec7a8 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,7 +27,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 589ea1c..d10fd1f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,7 +30,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5dfc69c..4ff518e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -195,7 +195,7 @@ register "DdiPort4Ddc" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 5959e79..a6bad13 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -132,7 +132,7 @@ # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index a0d38b3..922b673 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -95,7 +95,7 @@ # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 6776284..c01613c 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -70,7 +70,7 @@ register "tcss_aux_ori" = "4" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index bee71aa..012afc4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register "PcieClkSrcClkReq[5]" = "5" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 0ba9e83..e49c102 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -38,7 +38,7 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 59d69dc..1495366 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -150,7 +150,7 @@ }" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # GPIO for SD card detect register "sdcard_cd_gpio" = "VGPIO_39" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 010cae2..e97d19e 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -50,7 +50,7 @@ register "cnvi_bt_core" = "true" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index fb55da4..b864da6 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ register "sagv" = "SaGv_Enabled" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b82f583..69ec546 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -68,7 +68,7 @@ register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 51895b2..fbb8418 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -75,7 +75,7 @@ register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 1c4af58..580ca76 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -20,7 +20,7 @@ register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" # Display configuration (4 DPs) register "ddi_ports_config" = "{ diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 317de80..6e1ecfd 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -105,7 +105,7 @@ register "tcc_offset" = "1" # TCC of 99C # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" # Enable Turbo register "eist_enable" = "true" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index df0dbdf..10782b2 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -11,7 +11,7 @@ register "eist_enable" = "true" # Enable lpss s0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index f8e494a..c00404d 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/jasperlake register "eist_enable" = "true" - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index e26e6b2..cf1a8b8 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -19,7 +19,7 @@ register "PcieClkSrcClkReq[14]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[15]" = "PCIE_CLK_NOTUSED" - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "eist_enable" = "true" diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index 67bdf8e..fd6c590 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -15,7 +15,7 @@ register "eist_enable" = "true" # Enable s0ix, required for TGL-U - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 2227d1b..e3a23b2 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -128,7 +128,7 @@ uint32_t gen4_dec; /* Enable S0iX support */ - int s0ix_enable; + bool s0ix_enable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 4d4e2a1..630317a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -141,7 +141,7 @@ uint32_t gen4_dec; /* Enable S0iX support */ - int s0ix_enable; + bool s0ix_enable; /* S0iX: Selectively disable individual sub-states, by default all are enabled. */ enum lpm_state_mask LpmStateDisableMask; -- To view, visit https://review.coreboot.org/c/coreboot/+/84159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Gerrit-Change-Number: 84159 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83981/comment/4034f992_e44f8743?us… : PS4, Line 20: > > Please document the command. What was the output before, and what is it after the commit? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:00:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83981?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... soc/intel/common/gpio: support 16-bit CPU Port ID - Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. - Change cpu_port field to 16-bit width if the Kconfig is set. BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. The bit 15:8 of the returned port ID value should be 0xF2 instead of zero. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/cb61e844_616fc68a?us… : PS7, Line 25: #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) : : /* NOTE: For platform doesn't have support for GPE1, adding dummy entries here for common code : */ : #ifndef GPE1_STS : #define GPE1_STS(x) (0x0 + ((x) * 4)) : #endif : #ifndef GPE1_REG_MAX : #define GPE1_REG_MAX 0 : #endif : : #endif > we should avoid defining it across multiple files. […] The defines is moved to src/soc/intel/common/block/include/intelblocks/pmclib.h in https://review.coreboot.org/c/coreboot/+/84103/7 https://review.coreboot.org/c/coreboot/+/84104/comment/c30e4a9b_1f51ac48?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > can I request you to perform this renaming as part of the base CL and mention the motivation about w […] sure. working on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:51:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: tree: Use boolean for dmi_power_optimize_disable
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84158?usp=email ) Change subject: tree: Use boolean for dmi_power_optimize_disable ...................................................................... tree: Use boolean for dmi_power_optimize_disable Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/soc/intel/alderlake/chip.h 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84158/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 1cb6b5d..dd851e1 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -83,7 +83,7 @@ }" register "hybrid_storage_mode" = "true" - register "dmi_power_optimize_disable" = "1" + register "dmi_power_optimize_disable" = "true" # FIVR configuration register "fivr_rfi_frequency" = "1394" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index a613980..31ba6a3 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -13,7 +13,7 @@ register "pmc_gpe0_dw2" = "GPD" register "hybrid_storage_mode" = "true" - register "dmi_power_optimize_disable" = "1" + register "dmi_power_optimize_disable" = "true" # FIVR configuration register "fivr_rfi_frequency" = "1394" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c8005de..7e520bb 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -575,8 +575,8 @@ uint8_t cpu_ratio_override; /* - * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. - * Default 0. Setting this to 1 disables the DMI Power Optimizer. + * Enable/Disable DMI Power Optimizer on PCH side. + * Default is "false". */ bool dmi_power_optimize_disable; -- To view, visit https://review.coreboot.org/c/coreboot/+/84158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Gerrit-Change-Number: 84158 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Paul Menzel, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 10: (4 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/d385bb9d_39a02f4a?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > > Subrata, […] sure. agree. File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/3f05ab99_569628c6?us… : PS10, Line 132: platforms > u can specify from which SoC? Done https://review.coreboot.org/c/coreboot/+/84103/comment/5adf3e97_08b126bb?us… : PS10, Line 134: SOD > SoC? Done https://review.coreboot.org/c/coreboot/+/84103/comment/acbdec2c_b5e67852?us… : PS10, Line 138: : #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) : #define GPE1_STS(x) (0x0 + ((x) * 4)) : #define GPE1_REG_MAX 0 : #endif > please move the macros at line #9 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:44:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: tree: use boolean for hybrid_storage_mode
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84157?usp=email ) Change subject: tree: use boolean for hybrid_storage_mode ...................................................................... tree: use boolean for hybrid_storage_mode Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84157/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 68c0754..5959e79 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,7 +83,7 @@ }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ec60894..a0d38b3 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -76,7 +76,7 @@ }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 3c41f58..1cb6b5d 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -82,7 +82,7 @@ [DDI_PORT_4] = DDI_ENABLE_HPD, }" - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "1" # FIVR configuration diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index d087c3f..a613980 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -12,7 +12,7 @@ register "pmc_gpe0_dw1" = "GPP_VPGIO" register "pmc_gpe0_dw2" = "GPD" - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "1" # FIVR configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/84157?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Gerrit-Change-Number: 84157 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: tree: Use boolean for enable_c6dram
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Jeremy Soller, Kapil Porwal, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Pranava Y N, Sean Rhodes, Subrata Banik, Tim Crawford. Hello Jeremy Soller, Kapil Porwal, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Pranava Y N, Sean Rhodes, Subrata Banik, Tim Crawford, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84155?usp=email to look at the new patch set (#2). Change subject: tree: Use boolean for enable_c6dram ...................................................................... tree: Use boolean for enable_c6dram Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/protectli/vault_adl_p/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/pantherlake/chip.h M src/soc/intel/tigerlake/chip.h 22 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84155/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Gerrit-Change-Number: 84155 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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