coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Paul Menzel, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#13). Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 13 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Paul Menzel, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 11: (6 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/84103/comment/586da105_dfb1d194?us… : PS11, Line 80: e > nit […] Done File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/d1e0cd39_c2d5ac6c?us… : PS11, Line 108: fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); > move this at line #106? thx https://review.coreboot.org/c/coreboot/+/84103/comment/703266b2_582c82b7?us… : PS11, Line 109: !fadt->gpe1_blk > again same mistake. […] oh. no. thx https://review.coreboot.org/c/coreboot/+/84103/comment/cff57e2c_fc9b1bb7?us… : PS11, Line 110: gpe0_blk_len > shouldn't this be `fadt->gpe1_blk_len` fixed. also, GPE1_REG_MAX. https://review.coreboot.org/c/coreboot/+/84103/comment/79990b7f_25429890?us… : PS11, Line 115: 0 > should be `gpe1_blk_len` as per ACPI spec? […] Subrata, gp10_blk_en is correct since its starting bit is right after the end of gpe0. Also confirmed with BIOS code: #define EFI_ACPI_GPE1_BASE (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 2) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/a7fadbda_0c0a6c69?us… : PS11, Line 140: In addition, the following SOC GPE1 defines are required in common : * code but not present in older platform headers. Therefore, the dummy entries : * are added here for platforms without GPE1 support. > move this highlighted comment above line #11 as its applicable there Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 18:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: commonlib/coreboot_tables.h: Fix Wunterminated-string-initialization ...
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84170?usp=email ) Change subject: commonlib/coreboot_tables.h: Fix Wunterminated-string-initialization error ...................................................................... commonlib/coreboot_tables.h: Fix Wunterminated-string-initialization error This to fix: src/mainboard/google/geralt/panel.c:59:59: error: initializer-string for array of 'unsigned char' is too long [-Werror=unterminated-string-initialization] 59 | {GPIO_AP_DISP_BKLTEN.id, ACTIVE_HIGH, -1, "backlight enable"}, | ^~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Change-Id: I6fca7f067dab07bda5a31c9b5796272bea9763e1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/coreboot_tables.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/84170/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7cbc7da..5ebbe15 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -310,7 +310,7 @@ #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 uint32_t value; -#define GPIO_MAX_NAME_LENGTH 16 +#define GPIO_MAX_NAME_LENGTH 17 uint8_t name[GPIO_MAX_NAME_LENGTH]; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fca7f067dab07bda5a31c9b5796272bea9763e1 Gerrit-Change-Number: 84170 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83981/comment/2f4809f8_85939c03?us… : PS9, Line 12: BUG= > use `BUG=none` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 17:35:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83981?usp=email to look at the new patch set (#10). Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... soc/intel/common/gpio: support 16-bit CPU Port ID - Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. - Change cpu_port field to 16-bit width if the Kconfig is set. BUG=none TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. The bit 15:8 of the returned port ID value should be 0xF2 instead of zero. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: [RFC] Add UPL FDT handoff
by Maximilian Brune (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Arthur Heymans, Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Philipp Hug, Simon Glass, ron minnich. Hello Jakub Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Philipp Hug, Simon Glass, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76591?usp=email to look at the new patch set (#22). Change subject: [RFC] Add UPL FDT handoff ...................................................................... [RFC] Add UPL FDT handoff This adds another handoff that is basically the same as coreboot tables. The only real difference is that it uses the devicetree format to transfer the information to payload. This handoff is inspired by the UPL (universal payload) specification. Tested: start q35 qemu with coreinfo as payload and see that console still works and the devicetree is printed by coreboot. Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M payloads/Kconfig M payloads/libpayload/Kconfig M payloads/libpayload/arch/arm/coreboot.c M payloads/libpayload/arch/arm64/coreboot.c M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/Makefile.mk A payloads/libpayload/libc/upl_fdt.c M src/arch/arm/include/arch/cbconfig.h M src/arch/arm64/include/arch/cbconfig.h M src/arch/ppc64/include/arch/cbconfig.h M src/arch/riscv/include/arch/cbconfig.h M src/arch/x86/include/arch/cbconfig.h M src/arch/x86/tables.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/boot/coreboot_tables.h M src/include/boot/tables.h A src/include/boot/upl_fdt_table.h M src/lib/Makefile.mk M src/lib/bootmem.c M src/lib/coreboot_table.c A src/lib/tables.c A src/lib/upl_fdt_table.c M tests/lib/Makefile.mk 27 files changed, 662 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/76591/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/76591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Gerrit-Change-Number: 76591 Gerrit-PatchSet: 22 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: [for test] test upgrade crossgcc
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Cliff Huang, Lance Zhao, Martin L Roth, Tim Wawrzynczak. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81419?usp=email ) Change subject: [for test] test upgrade crossgcc ...................................................................... Patch Set 26: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 26 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 16:48:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: [for test] test upgrade crossgcc
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Cliff Huang, Lance Zhao, Martin L Roth, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Martin L Roth, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#26). Change subject: [for test] test upgrade crossgcc ...................................................................... [for test] test upgrade crossgcc Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-15-20240825_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20240825_gnat.patch R util/crossgcc/patches/gcc-15-20240825_libcpp.patch R util/crossgcc/patches/gcc-15-20240825_libgcc.patch R util/crossgcc/patches/gcc-15-20240825_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20240825_rv32iafc.patch D util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/cmake-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.30.3.tar.gz.cksum D util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20240825.tar.xz.cksum D util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/libunwind-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/lld-19.1.0-rc3.src.tar.xz.cksum D util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/llvm-19.1.0-rc3.src.tar.xz.cksum 25 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 26 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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