coreboot-gerrit August 2024

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[S] Change in coreboot[main]: tree: Use boolean for disable_package_c_state_demotion
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84164?usp=email ) Change subject: tree: Use boolean for disable_package_c_state_demotion ...................................................................... tree: Use boolean for disable_package_c_state_demotion Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb 13 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84164/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 4af0063..8904516 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -19,7 +19,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Disable C1 state auto-demotion for all brox baseboards register "disable_c1_state_auto_demotion" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 301a216..6160ebf 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -16,7 +16,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # DPTF enable register "dptf_enable" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index d2518d6..90677e4 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -92,7 +92,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index f3ad232..cbca871 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -142,7 +142,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 6fb91ff..ba97143 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -142,7 +142,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 7158b06..517d17b 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index e024680..b973cef 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 248844b..92f2f7f 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 7e17ab4..6df6c73 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb index 73012d1..8747164 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb index 8bc35c0..0c62e4c 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on device ref pch_espi on diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index fd2f4af..2dbceb9 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -56,7 +56,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable energy reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index b5926ef..d6b4650 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -21,7 +21,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on device ref system_agent on end -- To view, visit https://review.coreboot.org/c/coreboot/+/84164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Gerrit-Change-Number: 84164 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: tree: Use boolean for disable_c1_state_auto_demotion
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84163?usp=email ) Change subject: tree: Use boolean for disable_c1_state_auto_demotion ...................................................................... tree: Use boolean for disable_c1_state_auto_demotion Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 9 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/84163/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index ce39527..4af0063 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -22,7 +22,7 @@ register "disable_package_c_state_demotion" = "1" # Disable C1 state auto-demotion for all brox baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # DPTF enable register "dptf_enable" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index b583cc8..3009f65 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -80,7 +80,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brask baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 397e0f5..301a216 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -77,7 +77,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index a24b657..6bd659d 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -59,7 +59,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 6439c0e..7158b06 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index ccc6995..e024680 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 2d9f342..248844b 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 741d8a4..7e17ab4 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 23acba4..fd2f4af 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -53,7 +53,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/84163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Gerrit-Change-Number: 84163 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/alderlake: Prevent overlapping boot screens
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Amanda Hwang, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84144?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/alderlake: Prevent overlapping boot screens ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: will wait for @amanda_hwang@compal.corp-partner.google.com to verify this CL on Orisa -- To view, visit https://review.coreboot.org/c/coreboot/+/84144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9 Gerrit-Change-Number: 84144 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:23:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83981/comment/ff189b33_394c9bcd?us… : PS9, Line 12: BUG= use `BUG=none` -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:10:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Use boolean for PmTimerDisabled
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Elyes Haouas, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84162?usp=email ) Change subject: soc/intel/pantherlake: Use boolean for PmTimerDisabled ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/84162/comment/039cb574_77d29051?us… : PS1, Line 205: PmTimerDisabled this is camel case, hopefully @mishra.saurabh@intel.com pay attention to it -- To view, visit https://review.coreboot.org/c/coreboot/+/84162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4342cc2f375da5fcbadc2c5e716371f6447f6518 Gerrit-Change-Number: 84162 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:10:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Use boolean for PmTimerDisabled
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Elyes Haouas, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84162?usp=email ) Change subject: soc/intel/pantherlake: Use boolean for PmTimerDisabled ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4342cc2f375da5fcbadc2c5e716371f6447f6518 Gerrit-Change-Number: 84162 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:09:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 11: (6 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/84103/comment/49fb1b1c_fa2783df?us… : PS11, Line 80: e nit `Event` File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/1a716638_99be03bf?us… : PS11, Line 108: fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); move this at line #106? https://review.coreboot.org/c/coreboot/+/84103/comment/67d0f76f_c98eebef?us… : PS11, Line 109: !fadt->gpe1_blk again same mistake. ``` if (fadt->gpe1_blk) { ... } ``` https://review.coreboot.org/c/coreboot/+/84103/comment/f3ae8a3c_a0c753e6?us… : PS11, Line 110: gpe0_blk_len shouldn't this be `fadt->gpe1_blk_len` https://review.coreboot.org/c/coreboot/+/84103/comment/ad644eaa_032d83fd?us… : PS11, Line 115: 0 should be `gpe1_blk_len` as per ACPI spec? ``` GPE0_BLK_LEN 1 92 The length of the register whose address is given by X_GPE0_BLK (if nonzero) or by GPE0_BLK (otherwise) in bytes. The value is a non-negative multiple of 2. GPE1_BLK_LEN 1 93 The length of the register whose address is given by X_GPE1_BLK (if nonzero) or by GPE1_BLK (otherwise) in bytes. The value is a non-negative multiple of 2. GPE1_BASE 1 94 Offset within the ACPI general-purpose event model where GPE1 based events start ``` File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/cb0f521f_a6617c2b?us… : PS11, Line 140: In addition, the following SOC GPE1 defines are required in common : * code but not present in older platform headers. Therefore, the dummy entries : * are added here for platforms without GPE1 support. move this highlighted comment above line #11 as its applicable there -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Use boolean for PmTimerDisabled
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84162?usp=email ) Change subject: soc/intel/pantherlake: Use boolean for PmTimerDisabled ...................................................................... soc/intel/pantherlake: Use boolean for PmTimerDisabled Change-Id: I4342cc2f375da5fcbadc2c5e716371f6447f6518 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/pantherlake/chip.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/84162/1 diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 79d7f26..c31ec84 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -202,7 +202,7 @@ /* Enable C6 DRAM */ bool enable_c6dram; - uint8_t PmTimerDisabled; + bool PmTimerDisabled; /* * SerialIO device mode selection: * PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/84162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4342cc2f375da5fcbadc2c5e716371f6447f6518 Gerrit-Change-Number: 84162 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... tree: Use boolean for dptf_enable Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/aoostar/wtr_r1/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/pantherlake/chip.h M src/soc/intel/tigerlake/chip.h 55 files changed, 55 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/84161/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e489e25..d3f50ef 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -27,7 +27,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index a802cca..18109c8 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -12,7 +12,7 @@ register "sagv" = "SaGv_Enabled" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "s0ix_enable" = "true" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 59e297c..d999973 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -15,7 +15,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "PrimaryDisplay" = "Display_PEG" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index ad735ed..14ac280 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -22,7 +22,7 @@ register "eist_enable" = "true" # DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index b900af1..ce39527 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -25,7 +25,7 @@ register "disable_c1_state_auto_demotion" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 2ba54bc..b583cc8 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -18,7 +18,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index e07cf2a..397e0f5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,7 +19,7 @@ register "disable_package_c_state_demotion" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index f91b088..a24b657 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -15,7 +15,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 3d28ed3..d2518d6 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -32,7 +32,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ad5b943..f3ad232 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -27,7 +27,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 868342b..6fb91ff 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -27,7 +27,7 @@ register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d..2b55e7c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ register "DdiPortCDdc" = "1" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Power limit config register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 7238a06..23fc46d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 25, .tdp_pl2_override = 51, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0779c6..e959607 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -184,7 +184,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 2976deb..a00d01b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2d2e13c..005852d 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8c33f02..0b4558b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 138499c..671150d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ register "lpss_s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 04df902..a3bd3fa 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index feea932..f47876a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 139a3c8..256a661 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 363b614..3a04b51 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 97b0c20..7c92dee 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -21,7 +21,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3743385..4345f73 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2d1a509..3d2767c 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 08880cb..2eee315 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 1192a5f..1207bb3 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index df39932..8ec7861 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 022dc8b..cd257d0 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index f97614d..8002af0 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -43,7 +43,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index fd30ce7..7a712f9 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 2cfa075..6439c0e 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 18c4192..ccc6995 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 58c725e..2d9f342 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 9e8f870..741d8a4 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 7eec7a8..d245844 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,7 +28,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d10fd1f..8fe366d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,7 +31,7 @@ register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 4ff518e..2d2b431 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,7 +198,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable External Bypass register "external_bypass" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a6bad13..1a2788e 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -133,7 +133,7 @@ register "tcss_aux_ori" = "0" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index c01613c..1ea7334 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -17,7 +17,7 @@ register "sagv" = "SaGv_Enabled" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # eMMC HS400 register "emmc_enable_hs400_mode" = "1" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 7a46e10..dc0ae8a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "emmc_tx_cmd_cntl" = "0x1305" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override: 7.5W setting gives a run-time 6W actual # Set RAPL PL2 to 15W. diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 1495366..e4e7baa 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -116,7 +116,7 @@ }" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index be5ba44..6718d62 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "IoBufferOwnership" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 458f559..5b809a6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index e97d19e..23acba4 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -113,7 +113,7 @@ register "pch_hda_idisp_codec_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device ref igpu on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 69ec546..70adca6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -71,7 +71,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fbb8418..d1deea3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -78,7 +78,7 @@ register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 953c819..3291e1d 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -3,7 +3,7 @@ chip soc/intel/apollolake register "enable_vtd" = "1" - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 4f7d7eb..e3ef140 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -24,7 +24,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9b0357f..fd931e7 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -15,7 +15,7 @@ register "eist_enable" = "true" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" register "tcc_offset" = "5" # TCC of 95C diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b448f9..257bb8a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -35,7 +35,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 311d96c..02b358a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -16,7 +16,7 @@ register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e3a23b2..061621c 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -130,7 +130,7 @@ /* Enable S0iX support */ bool s0ix_enable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable; /* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 3872916..79d7f26 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -88,7 +88,7 @@ /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ uint8_t TcssD3ColdDisable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable; /* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 630317a..f0cecb3 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -149,7 +149,7 @@ uint8_t TcssD3HotDisable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable; /* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/3405a1ef_7ebe50bc?us… : PS7, Line 25: #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1) : : /* NOTE: For platform doesn't have support for GPE1, adding dummy entries here for common code : */ : #ifndef GPE1_STS : #define GPE1_STS(x) (0x0 + ((x) * 4)) : #endif : #ifndef GPE1_REG_MAX : #define GPE1_REG_MAX 0 : #endif : : #endif > The defines is moved to src/soc/intel/common/block/include/intelblocks/pmclib.h in https://review. […] correction: https://review.coreboot.org/c/coreboot/+/84103/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 09:04:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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