coreboot-gerrit August 2024

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[XS] Change in coreboot[main]: tree: Use eist_enable as bool for newly merged files
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Jeremy Soller, Michał Żygowski, Piotr Król, Sean Rhodes, Tim Crawford. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84156?usp=email ) Change subject: tree: Use eist_enable as bool for newly merged files ...................................................................... tree: Use eist_enable as bool for newly merged files Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/protectli/vault_adl_p/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/system76/mtl/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84156/1 diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index c2959f0..7cccc30 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 010567a..fc69a9c 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -13,7 +13,7 @@ register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" register "cnvi_bt_core" = "true" register "cnvi_bt_audio_offload" = "true" diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index 9a4cfb4..0bd6721 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Thermal register "tcc_offset" = "8" -- To view, visit https://review.coreboot.org/c/coreboot/+/84156?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Gerrit-Change-Number: 84156 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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[S] Change in coreboot[main]: tree: Use boolean for skip_ext_gfx_scan
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84155?usp=email ) Change subject: tree: Use boolean for skip_ext_gfx_scan ...................................................................... tree: Use boolean for skip_ext_gfx_scan Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/protectli/vault_adl_p/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/pantherlake/chip.h M src/soc/intel/tigerlake/chip.h 22 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84155/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 11a8749..5e93271 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -21,7 +21,7 @@ # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + #register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index e874679..3c41f58 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -6,7 +6,7 @@ # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 738c8a3..d087c3f 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -6,7 +6,7 @@ # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index f11dc6a..c2959f0 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -6,7 +6,7 @@ # Sagv Configuration register "sagv" = "SaGv_Enabled" register "RMT" = "0" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "common_soc_config" = "{ // Type-C PD I2C bus diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 01c5df7..fc06d4c 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -47,7 +47,7 @@ register "SkipExtGfxScan" = "1" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index a555394..87e5849 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -11,7 +11,7 @@ # }" # FSP Memory - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "sagv" = "SaGv_Enabled" # FSP Silicon diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index df8bd99..570c727 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -15,7 +15,7 @@ }" # FSP Memory - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "SaGv" = "SaGv_Enabled" # FSP Silicon diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 1144162..48f6fb3 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -17,7 +17,7 @@ # FSP Memory register "CnviBtCore" = "true" register "CnviBtAudioOffload" = "1" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "SaGv" = "SaGv_Enabled" # FSP Silicon diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 145dbc2..010567a 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -9,7 +9,7 @@ }" # FSP Memory - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" register "sagv" = "SaGv_Enabled" # FSP Silicon diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index f5b7a1f..bd8c35f 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -21,7 +21,7 @@ register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 4e27318..9f144a8 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -14,7 +14,7 @@ register "eist_enable" = "true" # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # Thermal register "tcc_offset" = "8" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 3a99ab4..56d50db 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -21,7 +21,7 @@ register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index ed0a520..0c87d3a 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -22,7 +22,7 @@ # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5760e66..565c7f7 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -21,7 +21,7 @@ register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index cc3c619..bf4b89a 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -21,7 +21,7 @@ register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7e3ef0c..cdc50e9 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -21,7 +21,7 @@ register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index dd4d597..b5926ef 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -14,7 +14,7 @@ register "eist_enable" = "true" # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # Thermal register "tcc_offset" = "8" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 2bda9dc..acf50d1 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -27,7 +27,7 @@ # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/tigerlake/fsp_params.c) # Acoustic settings diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d96249d..67bdf8e 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -19,7 +19,7 @@ # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # System Agent dynamic frequency support register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 1c5d720..9fbc526 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -22,7 +22,7 @@ # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register "enable_c6dram" = "true" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index d1dbe44..3872916 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -201,7 +201,7 @@ uint8_t eist_enable; /* Enable C6 DRAM */ - uint8_t enable_c6dram; + bool enable_c6dram; uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 97fd275..4d4e2a1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -288,7 +288,7 @@ bool eist_enable; /* Enable C6 DRAM */ - uint8_t enable_c6dram; + bool enable_c6dram; /* * SerialIO device mode selection: -- To view, visit https://review.coreboot.org/c/coreboot/+/84155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Gerrit-Change-Number: 84155 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: tree: Use boolean for skip_ext_gfx_scan
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84154?usp=email ) Change subject: tree: Use boolean for skip_ext_gfx_scan ...................................................................... tree: Use boolean for skip_ext_gfx_scan Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/soc/intel/pantherlake/chip.h 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/84154/1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 7cb10d2..c0ef101 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -70,7 +70,7 @@ register "energy_perf_pref_value" = "0x73" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 7358eeb..f0f9598 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -68,7 +68,7 @@ register "sagv_gear[3]" = "2" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 00acbec..7626083 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -70,7 +70,7 @@ register "energy_perf_pref_value" = "0x73" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 625a36b..d3038f5 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -65,7 +65,7 @@ register "sagv_gear[3]" = "2" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 589ce14..d1dbe44 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -179,7 +179,7 @@ IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, } IgdDvmt50PreAlloc; - uint8_t skip_ext_gfx_scan; + bool skip_ext_gfx_scan; /* CNVi WiFi Core Enable/Disable */ bool cnvi_wifi_core; -- To view, visit https://review.coreboot.org/c/coreboot/+/84154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Gerrit-Change-Number: 84154 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83981/comment/f3ef12c3_c8672be2?us… : PS4, Line 20: > Please document the command. What was the output before, and what is it after the commit? @cliff.huang@intel.com can you please address this review comment ? almost like 10 days old ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: tree: Drop unnecessary "true/false" comments
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun, Werner Zeh, Yu-Ping Wu. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84152?usp=email ) Change subject: tree: Drop unnecessary "true/false" comments ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/84152/comment/d62e44e6_5df00f52?us… : PS1, Line 111: Rank Margin Tool > I would keep this part Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/84152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Gerrit-Change-Number: 84152 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:05:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 10: (3 comments) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/1f5c6bb0_3fc4cb9e?us… : PS10, Line 132: platforms u can specify from which SoC? https://review.coreboot.org/c/coreboot/+/84103/comment/cf17bc17_c68581f3?us… : PS10, Line 134: SOD SoC? https://review.coreboot.org/c/coreboot/+/84103/comment/1b35f9cb_60ee36dc?us… : PS10, Line 138: : #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) : #define GPE1_STS(x) (0x0 + ((x) * 4)) : #define GPE1_REG_MAX 0 : #endif please move the macros at line #9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:05:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 10: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/8eb53f0b_1a369903?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > Subrata, > > agree. We will need only _HAVE_GPE1 flag as long as the SOC header uses _HVAE_GPE1 flag for providing GPE1 defines. For the case of not using GPE1 in PTL, we will unset this flag. yes, that makes more sense to me. but note if you wish to make `_HAVE_GPE1` Kconfig configurable then better to select from mainboard and not SoC default. https://review.coreboot.org/c/coreboot/+/84103/comment/e5fac0a3_01b563a3?us… : PS7, Line 128: 8 > yes. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:03:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: tree: Drop unnecessary "true/false" comments
by Angel Pons (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Elyes Haouas, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun, Werner Zeh, Yu-Ping Wu. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84152?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: tree: Drop unnecessary "true/false" comments ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/84152/comment/ab4e39f7_6a55b674?us… : PS1, Line 111: Rank Margin Tool I would keep this part https://review.coreboot.org/c/coreboot/+/84152/comment/06214ee8_4ed990b2?us… : PS1, Line 266: HDP This should be HPD (Hot Plug Detect). Fixing this would be out of scope for this change, though File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/84152/comment/39d50592_96d90cd2?us… : PS1, Line 290: /* Enable C6 DRAM */ : uint8_t enable_c6dram; For another patch: this should also be a `bool` -- To view, visit https://review.coreboot.org/c/coreboot/+/84152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Gerrit-Change-Number: 84152 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 31 Aug 2024 08:01:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Doc/mainboard/hp: Use archive URL for HP Sure Start Whitepaper
by Nicholas Sudsgaard (Code Review) 31 Aug '24

31 Aug '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84153?usp=email ) Change subject: Doc/mainboard/hp: Use archive URL for HP Sure Start Whitepaper ...................................................................... Doc/mainboard/hp: Use archive URL for HP Sure Start Whitepaper The original URL now redirects to "Page Not Found". Change-Id: I696c758ff68d961054d4994177a1e1d1b88170aa Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/hp/hp_sure_start.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84153/1 diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md index a07d9d0..9cf8469 100644 --- a/Documentation/mainboard/hp/hp_sure_start.md +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -57,4 +57,4 @@ we can leave it untouched, and do not need to extract the EC firmware to put it in the coreboot image. -[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 +[HP Sure Start Technical Whitepaper]: https://web.archive.org/web/20230610031120/http://h10032.www1.hp.com/ctg/Ma… -- To view, visit https://review.coreboot.org/c/coreboot/+/84153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I696c758ff68d961054d4994177a1e1d1b88170aa Gerrit-Change-Number: 84153 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Paul Menzel, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 9: (3 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/84103/comment/3d637eb2_3dfc0da9?us… : PS9, Line 83: Requires define GPE1_STS(0) and GPE1_REG_MAX from the SOC header. > Please add a blank line above. not sure if we can have a bank line under 'help'. But let me re-arrange the desciption. https://review.coreboot.org/c/coreboot/+/84103/comment/a67b8e46_795704a8?us… : PS9, Line 89: for > to Done https://review.coreboot.org/c/coreboot/+/84103/comment/3e402da5_9e89568a?us… : PS9, Line 90: that publishes > … that publish … or … publishing … Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 31 Aug 2024 07:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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