coreboot-gerrit August 2024

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[M] Change in coreboot[main]: tree: Drop unnecessary "true/false" comments
by Elyes Haouas (Code Review) 31 Aug '24

31 Aug '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84152?usp=email ) Change subject: tree: Drop unnecessary "true/false" comments ...................................................................... tree: Drop unnecessary "true/false" comments Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/security/vboot/misc.h M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/tigerlake/chip.h 8 files changed, 5 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84152/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index a7069f3..1b66186 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -22,9 +22,6 @@ /* * Check if given flag is set in the flags field in GBB header. - * Return value: - * true: Flag is set. - * false: Flag is not set. */ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index ec6c0f5..c8005de 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -466,11 +466,7 @@ } igd_dvmt50_pre_alloc; bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram; /* diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 97657e2..9459b88 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,10 +237,7 @@ /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram; /* diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index f140fc8..dc27d51 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -14,21 +14,10 @@ * 3. SOC will allow common code to set UART into legacy mode if supported. */ -/* - * Check if UART debug controller is initialized - * Returns: - * true = If debug controller PCI config space is initialized and device is - * out of reset - * false = otherwise - */ bool uart_is_controller_initialized(void); /* * Check if dev corresponds to UART debug port controller. - * - * Returns: - * true: UART dev is debug port - * false: otherwise */ bool uart_is_debug_controller(struct device *dev); diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e5c7f54..2227d1b 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -258,7 +258,6 @@ uint8_t Heci2Enable; uint8_t Heci3Enable; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 542ccb6..a012b6d 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -108,11 +108,6 @@ SaGv_Enabled, } SaGv; - /* Rank Margin Tool - * - * true: Enable - * false: Disable - */ bool RMT; /* USB related */ @@ -178,7 +173,6 @@ /* Gfx related */ bool SkipExtGfxScan; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -263,10 +257,8 @@ uint8_t DdiPortAConfig; uint8_t DdiPortBConfig; - /* HDP config - * - * true: Enable HDB - * false: Disable HDP + /* + * HDP config */ bool DdiPortAHpd; bool DdiPortBHpd; @@ -276,10 +268,8 @@ bool DdiPort3Hpd; bool DdiPort4Hpd; - /* DDC config - * - * true: Enable DDC - * false: Disable DDC + /* + * DDC config */ bool DdiPortADdc; bool DdiPortBDdc; @@ -411,9 +401,6 @@ /* * Enable or Disable Acoustic Noise Mitigation feature. - * - * false: Disabled - * true: Enabled */ bool AcousticNoiseMitigation; diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index e76f169..bf7bd36 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -209,7 +209,7 @@ SAGV_POINTS_0_1_2_3 = 0x0f, } sagv_wp_bitmap; - /* Rank Margin Tool. true:Enable, false:Disable */ + /* Rank Margin Tool. */ bool rmt; /* USB related */ @@ -297,8 +297,6 @@ } igd_dvmt50_pre_alloc; bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e8d417e..97fd275 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,8 +285,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -504,29 +502,8 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; - - /* - * External Clock Gate - * true = Mainboard design uses external clock gating - * false = Mainboard design does not use external clock gating - * - */ bool external_clk_gated; - - /* - * External PHY Gate - * true = Mainboard design uses external phy gating - * false = Mainboard design does not use external phy gating - * - */ bool external_phy_gated; - - /* - * External Bypass Enable - * true = Mainboard design uses external bypass rail - * false = Mainboard design does not use external bypass rail - * - */ bool external_bypass; /* i915 struct for GMA backlight control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Gerrit-Change-Number: 84152 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: mb/system76/rpl: bonw15: Update GPIOs
by Paul Menzel (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Paul Menzel has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/84149?usp=email ) Change subject: mb/system76/rpl: bonw15: Update GPIOs ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84149/comment/0248d16e_0677b1b2?us… : PS1, Line 7: Update GPIOs Maybe more specific: > Mark non-functions GPIOs as unconnected (No idea if the terms are correct.) https://review.coreboot.org/c/coreboot/+/84149/comment/4255b38a_79ff6e5d?us… : PS1, Line 9: schematics If they have a version, please document it. -- To view, visit https://review.coreboot.org/c/coreboot/+/84149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a81115850d7bf3ecabeae29058e86cea51ac390 Gerrit-Change-Number: 84149 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 05:11:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/8c8d2cf4_c0119b2d?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > okay. […] Subrata, agree. We will need only _HAVE_GPE1 flag as long as the SOC header uses _HVAE_GPE1 flag for providing GPE1 defines. For the case of not using GPE1 in PTL, we will unset this flag. -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sat, 31 Aug 2024 00:58:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/8fe42da8_adb0611d?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > > Subrata, […] okay. At this time, we do want to keep the flag to switch between _USE_GPE1=0 and 1 for PTL at this time. There are things still under development/validation. All individual GPE1 will need to checked and this is still in progress. let me make another change. https://review.coreboot.org/c/coreboot/+/84103/comment/3fd8a038_8141d93b?us… : PS7, Line 128: 8 > > The unit for gpe1_base is bit and GPE0 block size is in bytes. […] yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 22:30:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 31 Aug '24

31 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>

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[M] Change in coreboot[main]: vendorcode/intel: allow selecting EDK headers manually
by Sergii Dmytruk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Martin L Roth, Ronak Kanabar. Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83738?usp=email ) Change subject: vendorcode/intel: allow selecting EDK headers manually ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/intel/Kconfig: https://review.coreboot.org/c/coreboot/+/83738/comment/df7f2e45_b5cc21bf?us… : PS3, Line 34: PAYLOAD_EDK2 > Just thinking here, so feel free to ignore this. […] Are you proposing to reverse the dependency? I.e. add something like this here (unless there is a more suitable file): ``` config UEFI_PAYLOAD def_bool n help Select this in a payload to indicate that it follows UEFI specification. ``` Use `UEFI_PAYLOAD` instead of `PAYLOAD_EDK2` in this file and update `payloads/external/edk2/Kconfig`: ``` config PAYLOAD_EDK2 ... select UEFI_PAYLOAD ... ``` Not sure there will be non-EDK2 UEFI payload, but this solution would be cleaner if I understood it correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/83738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I964142ef64967b4c9b329025ebcad701e34a5035 Gerrit-Change-Number: 83738 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 21:48:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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[S] Change in coreboot[main]: Documentation/drivers/smmstorev2.md: describe capsule update API
by Sergii Dmytruk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Patrick Rudolph. Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83426?usp=email ) Change subject: Documentation/drivers/smmstorev2.md: describe capsule update API ...................................................................... Patch Set 6: (1 comment) File Documentation/drivers/smmstorev2.md: https://review.coreboot.org/c/coreboot/+/83426/comment/965727fb_11dea9cc?us… : PS5, Line 221: It is expected that the : payload won't allow regular OS to boot if the handler is enabled without : rebooting first. > Sorry about all the questions here: […] Please see updated version in which I tried to address your questions. -- To view, visit https://review.coreboot.org/c/coreboot/+/83426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94761d18be567e5302d1a836f09f0a7eecb4fb00 Gerrit-Change-Number: 83426 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 30 Aug 2024 21:34:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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[S] Change in coreboot[main]: Documentation/drivers/smmstorev2.md: describe capsule update API
by Sergii Dmytruk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Sergii Dmytruk. Hello Arthur Heymans, Krystian Hebel, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83426?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation/drivers/smmstorev2.md: describe capsule update API ...................................................................... Documentation/drivers/smmstorev2.md: describe capsule update API This commit adds a description of capsule update commands implemented in SMMSTORE in previous patches. Change-Id: I94761d18be567e5302d1a836f09f0a7eecb4fb00 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M Documentation/drivers/smmstorev2.md 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/83426/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/83426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94761d18be567e5302d1a836f09f0a7eecb4fb00 Gerrit-Change-Number: 83426 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[S] Change in coreboot[main]: [Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo
by Dinesh Gehlot (Code Review) 30 Aug '24

30 Aug '24

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84151?usp=email ) Change subject: [Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo ...................................................................... [Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo Change-Id: Ia4aaaa27d8a60ca9972f99b32597eef386cc365e Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/84151/1 diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index 1651b08..63a5086 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -34,8 +34,8 @@ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ PAD_NC(GPP_A15, NONE), - /* A16 : USB_OC3# ==> NC */ - PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), + /* A16 : [NF1: USB_OC3# NF4: ISH_GP5 NF6: USB_C_GPP_A16] ==> ISH_MODE_ANGLE_2 */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4), /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT), /* A18 : DDSP_HPDB ==> DDI2_HPD */ @@ -117,14 +117,14 @@ /* C7 : SML1_SMBDATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), - /* D0 : ISH_GP0 ==> SOC_GSEN1_INT# */ + /* D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> SOC_GSEN1_INT# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), - /* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */ + /* D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> SOC_GSEN2_INT# */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), - /* D2 : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */ - PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG), - /* D3 : NC */ - PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> SEN_MODE_EC_PCH_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D2, NONE, PLTRST, LEVEL, INVERT), + /* D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> SOC_TOF_INT# */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* D4 : NC */ PAD_NC(GPP_D4, NONE), /* D5 : NC */ @@ -176,8 +176,8 @@ PAD_NC(GPP_E7, NONE), /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* E9 : NC */ - PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), + /* E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> ISH_MODE_ANGLE_1 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2), /* E10 : NC */ PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4aaaa27d8a60ca9972f99b32597eef386cc365e Gerrit-Change-Number: 84151 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>

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coreboot-gerrit August 2024