coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brox/jubilant: I2C signal tuning
by Bob Moragues (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Kenneth Chan, Nick Vaccaro, Ren Kuo. Bob Moragues has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84143?usp=email ) Change subject: mb/google/brox/jubilant: I2C signal tuning ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356 Gerrit-Change-Number: 84143 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 17:19:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/depthcharge: Add default 64-bit libpayload config
by Cliff Huang (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Martin L Roth, Paul Menzel, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84107?usp=email ) Change subject: payloads/depthcharge: Add default 64-bit libpayload config ...................................................................... Patch Set 7: (1 comment) File payloads/libpayload/configs/defconfig_64: https://review.coreboot.org/c/coreboot/+/84107/comment/0545fc7c_5dc5d829?us… : PS6, Line 1: CONFIG_LP_CHROMEOS=y > Do we need this config? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060 Gerrit-Change-Number: 84107 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Aug 2024 17:17:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config option
by Bob Moragues (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Bob Moragues, Eran Mitrani, Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo, Ren Kuo, Subrata Banik. Bob Moragues has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84095?usp=email ) Change subject: mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config option ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a Gerrit-Change-Number: 84095 Gerrit-PatchSet: 8 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 17:17:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/depthcharge: Add default 64-bit libpayload config
by Cliff Huang (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Martin L Roth, Paul Menzel, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Martin L Roth, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84107?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: payloads/depthcharge: Add default 64-bit libpayload config ...................................................................... payloads/depthcharge: Add default 64-bit libpayload config Add CONFIG_LP_DEFCONFIG_OVERRIDE_X64 flag to select default 64-bit config file in payloads/libpayload/configs directory. This is used in standalone environment. The existing libpayload deconfig file is for boards with 32-bit format and deconfig_64 file is added for 64-bit without adding specific board.[board name] file in libpayload. BUG=none TEST=Build with this new flag and check that the libpayload and depthcharge.elf are built in 64-bit format. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060 --- M payloads/external/Makefile.mk M payloads/external/depthcharge/Kconfig M payloads/external/depthcharge/Makefile A payloads/libpayload/configs/defconfig_64 4 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/84107/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060 Gerrit-Change-Number: 84107 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Jérémy Compostella (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... Patch Set 11: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/a6e2f38b_7f04c2d2?us… : PS10, Line 7: NEM+ > This (with +) is not mentioned in the commit message body. Done https://review.coreboot.org/c/coreboot/+/83946/comment/5424a5af_f07cad29?us… : PS10, Line 7: Use the effective way size for NEM+ > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/83946/comment/840e6fd6_d820eb54?us… : PS10, Line 10: the : way size which should be considered for No-Eviction Mode (NEM) : purposes > Add a comma at the end? Done https://review.coreboot.org/c/coreboot/+/83946/comment/ebc2f719_b0c565c0?us… : PS10, Line 21: has been > is Done https://review.coreboot.org/c/coreboot/+/83946/comment/62e15d90_4cbbdb20?us… : PS10, Line 25: TEST=Verified on PTL Intel reference platform > How? List the way size before and after? Done File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/83946/comment/2a987603_e7c775a6?us… : PS10, Line 84: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE > I would misinterpret it, that platforms not selecting this use an *in*effective way size, but from y […] Your interpretation is correct, I modified the commit message to avoid this confusion. https://review.coreboot.org/c/coreboot/+/83946/comment/fda9307f_41065be4?us… : PS10, Line 87: On some platforms > List the known ones? Done https://review.coreboot.org/c/coreboot/+/83946/comment/492603cd_fddd2662?us… : PS10, Line 87: the way size : which should be considered for eNEM purposes > Add a comma at the end? Done File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/83946/comment/2a1fdb96_16a724ac?us… : PS4, Line 498: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE > why would we consider the # of active cores ? This is just about complying with the ADL EDS or the M […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Aug 2024 17:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel: Use NEM+ effective way size for for ADL, MTL and PTL
by Jérémy Compostella (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pranava Y N, Rishika Raj, Sowmya Aralguppe, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83947?usp=email ) Change subject: soc/intel: Use NEM+ effective way size for for ADL, MTL and PTL ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83947/comment/32237bed_6431da75?us… : PS11, Line 7: for the right platforms > … for ADL, MTL, PTL Done https://review.coreboot.org/c/coreboot/+/83947/comment/7217187d_d27d9cf9?us… : PS11, Line 9: uses > use Done https://review.coreboot.org/c/coreboot/+/83947/comment/98ffbec8_591865b0?us… : PS11, Line 11: Mode > Fits on the line above? Done https://review.coreboot.org/c/coreboot/+/83947/comment/d9f2aa63_6a5a550b?us… : PS11, Line 14: TEST=Verified on PTL Intel reference platform > How? Added to the previous patch commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/83947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Gerrit-Change-Number: 83947 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 17:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Jérémy Compostella (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim. Hello Sowmya Aralguppe, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83946?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Sowmya Aralguppe, Code-Review+1 by Wonkyu Kim, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ On Alder Lake, Meteor Lake and Panther Lake platforms the way size to consider for NEM+ computation is the effective way size. On Alder Lake, the External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides a way to compute the effective way size by reading the number of CBO. Unfortunately, reading the number of CBO is not possible on Meteor Lake and Panther Lake. Therefor, we instead compute the effective way size as the biggest of power of two of the way size which works across all three platforms. The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to control this behavior. The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB). The number of ways that used to be computed is round(0x400000 / 0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000 NEM+ region. When the bootblock code accesses memory between 3 MB and 4 MB, the core would raise a page fault exception. The right computation is: 0x400000 / eff_way_size(0x100000) = 4. 4 ways needs to be mapped to cover the entire 0x400000 NEM+ region. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83946/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel: Use NEM+ effective way size for for ADL, MTL and PTL
by Jérémy Compostella (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Sowmya Aralguppe, Subrata Banik, Tarun, Wonkyu Kim. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj, Sowmya Aralguppe, Subrata Banik, Tarun, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83947?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Code-Review+1 by Sowmya Aralguppe, Code-Review+1 by Wonkyu Kim, Verified+1 by build bot (Jenkins) Change subject: soc/intel: Use NEM+ effective way size for for ADL, MTL and PTL ...................................................................... soc/intel: Use NEM+ effective way size for for ADL, MTL and PTL Alder Lake, Meteor Lake and Panther Lake use the effective way size when setting up the Enhanced No-Eviction Mode (cf. `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE'). BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/pantherlake/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83947/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/83947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Gerrit-Change-Number: 83947 Gerrit-PatchSet: 12 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 7: (3 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/2ef8adcd_7cbcca9e?us… : PS5, Line 29: GPE1_STS > > Subrata, […] Sure. Let me make the change. File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/2ebc780e_7791a932?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > ``` […] Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/8b04045d_2056d557?us… : PS7, Line 128: 8 > can you please explain why this is `8` I assume this is like `GPE1_REG_MAX` aka 4 and then two sets […] The unit for gpe1_base is bit and GPE0 block size is in bytes. The resulting is 0x80 (128), which is the next bit of GPE0 [127-0]. -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 16:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/system76/mtl: darp10: Add TCSS configs
by Tim Crawford (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Hello Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83696?usp=email to look at the new patch set (#2). Change subject: mb/system76/mtl: darp10: Add TCSS configs ...................................................................... mb/system76/mtl: darp10: Add TCSS configs Fixes using USB3 devices at USB3 speeds in all ports. This fix requires `EnableTcssCovTypeA`, which is not available in the coreboot FSP headers and not available upstream as Intel still has not made a Client FSP release. Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/mtl/variants/darp10/overridetree.cb M src/mainboard/system76/mtl/variants/darp10/ramstage.c 2 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83696/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e Gerrit-Change-Number: 83696 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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