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Hello Jeremy Soller,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83696?usp=email
to look at the new patch set (#2).
Change subject: mb/system76/mtl: darp10: Add TCSS configs
......................................................................
mb/system76/mtl: darp10: Add TCSS configs
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel still has not
made a Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/mtl/variants/darp10/overridetree.cb
M src/mainboard/system76/mtl/variants/darp10/ramstage.c
2 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83696/2
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Change subject: vendorcode/intel: allow selecting EDK headers manually
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/83738/comment/c9ccad98_e3b47008?us… :
PS3, Line 34: PAYLOAD_EDK2
Just thinking here, so feel free to ignore this.
I'm not a huge fan of requiring a specific payload be built at the same time as coreboot to enable coreboot functionality. It might make sense to add something to the payloads to say "This is the intended payload, but don't build it and include it in the image right now."
Any feelings about that?
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Change subject: drivers/usb/acpi: Add DSM for Intel Bluetooth
......................................................................
Patch Set 3:
(4 comments)
File src/drivers/usb/acpi/chip.h:
https://review.coreboot.org/c/coreboot/+/84133/comment/edd28b1d_e883830c?us… :
PS3, Line 51: bool intel_bt;
can you please use a meaningful name ? I don't understand what you mean by `intel_bt` ? is it like `is_bt_vendor_intel`?
File src/drivers/usb/acpi/usb_acpi.c:
https://review.coreboot.org/c/coreboot/+/84133/comment/62a3288e_7c155c2f?us… :
PS3, Line 12:
just one space to start the comment
https://review.coreboot.org/c/coreboot/+/84133/comment/852daf8f_83a617cc?us… :
PS3, Line 27: 0x03
can you please explain the meaning of hard coded value ?
https://review.coreboot.org/c/coreboot/+/84133/comment/cedc4416_5fdf9930?us… :
PS3, Line 36: /* aa10f4e0-81ac-4233-abf6-3b2ac50e28d9 */
unable to follow why you have used the GUID here ?
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Change subject: Documentation/drivers/smmstorev2.md: describe capsule update API
......................................................................
Patch Set 5:
(1 comment)
File Documentation/drivers/smmstorev2.md:
https://review.coreboot.org/c/coreboot/+/83426/comment/fdd1d5aa_25b5b04d?us… :
PS5, Line 221: It is expected that the
: payload won't allow regular OS to boot if the handler is enabled without
: rebooting first.
Sorry about all the questions here:
Why would this be expected?
How is this information passed to the payload?
What payloads would support this?
How is it enforced?
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Change subject: drivers/smmstore: add logic to disable capsule update handling code
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Patch Set 6: Code-Review+2
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Change subject: drivers/smmstore: add ability to write to whole flash
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Patch Set 5: Code-Review+2
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Change subject: drivers/smmstore: add ability to write to whole flash
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/smmstore/store.c:
https://review.coreboot.org/c/coreboot/+/83424/comment/2e095796_02199a1a?us… :
PS5, Line 49: if (*cmd & SMMSTORE_CMD_USE_FULL_FLASH) {
> Can we add a check to make sure that we're actually doing a capsule update before enabling this inst […]
Oh, I guess I should have looked at the next commit in the patch train.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 75:
(5 comments)
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/e53ba525_344c2817?us… :
PS23, Line 56: 0xBAC
> Subrata, should we have soc/tcss.h provides the defines needed for the hard-coded offsets in this file and the other two tcss asl files?
if u feel these macros have scope just beyond ASL file then add into some common TCSS.h file or local to this file also works
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/7888816c_45df4bf4?us… :
PS75, Line 27:
single tab ?
https://review.coreboot.org/c/coreboot/+/83772/comment/8126ea68_43bb0356?us… :
PS75, Line 28: ,
same
https://review.coreboot.org/c/coreboot/+/83772/comment/d6b57646_bb61c27b?us… :
PS75, Line 29:
same
https://review.coreboot.org/c/coreboot/+/83772/comment/c164ee41_0a2ffa24?us… :
PS75, Line 32: Offset (0x404),
: LSOE, 1,
: LNSE, 1,
same
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Change subject: drivers/smmstore: add ability to write to whole flash
......................................................................
Patch Set 5:
(2 comments)
File src/drivers/smmstore/store.c:
https://review.coreboot.org/c/coreboot/+/83424/comment/021441be_1bb24d3a?us… :
PS5, Line 44: use_full_flash
Nit: smstore_use_full_flash?
https://review.coreboot.org/c/coreboot/+/83424/comment/8876f273_1770b2ec?us… :
PS5, Line 49: if (*cmd & SMMSTORE_CMD_USE_FULL_FLASH) {
Can we add a check to make sure that we're actually doing a capsule update before enabling this instead of just that the capsule update code is built in?
Can we disable the bit again after the capsule update is completed?
This seems like it could be a security gap otherwise. I could be mistaken about this, but it just seems like we don't need to leave this enabled all the time either way.
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