Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84147?usp=email )
Change subject: mb/google/zork: Ensure early GPIOs programmed w/o vboot
......................................................................
mb/google/zork: Ensure early GPIOs programmed w/o vboot
Now that zork can boot without vboot, ensure that the GPIOs set in
verstage are programmed in bootblock on the non-vboot path. Use
the mb_set_up_early_espi() function similar to google/guybrush
implementation. This fixes the keyboard not working on non-vboot
builds.
TEST=build/boot google/zork (morphius) w/o vboot, verify keyboard
functional.
Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/zork/bootblock.c
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84147/1
diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c
index 022a5e0..fb6c8aa 100644
--- a/src/mainboard/google/zork/bootblock.c
+++ b/src/mainboard/google/zork/bootblock.c
@@ -3,8 +3,31 @@
#include <bootblock_common.h>
#include <baseboard/variants.h>
#include <acpi/acpi.h>
+#include <amdblocks/espi.h>
-void bootblock_mainboard_early_init(void)
+void mb_set_up_early_espi(void)
+{
+ size_t num_gpios;
+ const struct soc_amd_gpio *gpios;
+
+ /*
+ * The GPIOs below would normally be programmed in verstage, but
+ * if we're not using PSP verstage, need to set them up here instead.
+ */
+ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+ return;
+
+ gpios = variant_espi_gpio_table(&num_gpios);
+ gpio_configure_pads(gpios, num_gpios);
+
+ gpios = variant_tpm_gpio_table(&num_gpios);
+ gpio_configure_pads(gpios, num_gpios);
+
+ gpios = variant_early_gpio_table(&num_gpios);
+ gpio_configure_pads(gpios, num_gpios);
+}
+
+void bootblock_mainboard_init(void)
{
size_t num_gpios;
const struct soc_amd_gpio *gpios;
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Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
......................................................................
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Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
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Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
Would anyone please be able to review?
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